README.md
# BLE pedometer — fully routed with stock Pipeline 9
The complete 42 × 26 mm, four-layer PCB routes with **zero raw DRC errors**: 52 components, 138 traces and 122 vias. The cold-cache `tsci build --site` passed on 2026-09-05. TypeScript, logical design, fresh DRC and trace-continuity checks pass. See [VALIDATION.md](VALIDATION.md) and [validation.json](validation.json) for the exact result and remaining warnings.
The design retains the CC2340R5, BQ25150, BQ27427, BMA400, switched SPI OLED connector and five-pin JST-SH programming connector. It uses stock `beta_pipeline9` at 100× effort in one full-board pass. There are no autorouting phases, breakout directives, custom algorithms or modified routing engines. Ordinary placement groups organize the regions; selected source-defined fanouts and traces resolve the dense areas. [REGIONAL_ROUTING.md](REGIONAL_ROUTING.md) records the trials.
## Build and inspect
```sh
bun install --frozen-lockfile
bun run typecheck
bun run build --site --autorouter-debug --autorouter-dump-srj all --autorouter-timeout 600s
```
The wrapper runs the project's local tsci CLI, clears generated routing caches, validates the unmodified emitted circuit JSON, and refreshes PCB/schematic images and review BOM/placement CSVs. Open `dist/index.html` for the interactive PCB viewer. No generated copper is patched and no errors are filtered. Exact dependencies are recorded in `bun.lock`.
## Crystal routing
Both X48P and X48N now route entirely on top with zero vias, at 3.137 mm and 3.268 mm respectively. Y1 is rotated to 315° and positioned at (9, 0) mm. Trace-level via-count limits enforce these results; the full board passes raw DRC. See CRYSTAL_ROUTING.md.
## Programming connector
J4 is JST BM05B-SRSS-TB(LF)(SN), five-pin SH, 1 mm pitch. Custom pinout: 1 SWDIO, 2 SWCLK, 3 RESET_N, 4 GND, 5 VTREF. Pin 5 is target-voltage sense, not a probe power input. See DESIGN.md for the harness map.
## Hardware status
Routing completion is not hardware qualification. The board uses 0.10/0.20 mm vias, blind/buried spans and 0.05 mm clearance rules; the fabricator must approve the HDI stackup. Footprint/supplier warnings, antenna placement and RF impedance/matching still require review. Firmware, RF measurements and measured battery life remain outstanding; see DESIGN.md and ASSEMBLY.md. The short MCU-to-C21 RF trace is 0.12 mm; other RF sections remain 0.18 mm, pending stackup-specific impedance design.
Older routing experiments and custom-router reference files are archived outside this package in the workspace's `work/region-board/archived-project-artifacts/`. The separate `pedometer-rev-c-reference.zip` preserves the previous deliverable.
