seveibar/pedometer

This hardware setup integrates a Type-C connector, battery, display, and RF antenna connected through a microcontroller, USB interface, charging and fuel gauge ICs, along with associated passive components, enabling power management, data communication, and signal processing.

Version
0.4.4
License
unset
Stars
1

PIPELINE9_ONLY.md

> Historical experiment log. The active full-board design now passes raw DRC; see VALIDATION.md and REGIONAL_ROUTING.md. Referenced experiment files are archived outside the package in work/region-board/archived-project-artifacts/.

# Pipeline 9 only — incremental routing

The active design no longer imports or invokes custom `algorithmFn` callbacks. All signal-routing phases use `beta-pipeline9`; the board explicitly selects `beta_pipeline9`. Existing built-in power/ground fanout phases remain.

The previous custom callback source and tests are preserved only as historical material under `region-experiments/custom-reference/`. They are excluded from the active build.

Each trial clears routing caches and records its source, solver input/output, phase image and log. Raw DRC remains authoritative; no error filtering or post-build geometry patch is used.

| Trial | Change | Result |
| --- | --- | --- |
| 00-baseline | Replace all four custom callbacks with Pipeline 9 | Interrupt fails after seven completed phases |
| 01-interrupt-first | Move only interrupt to phase −1 | Interrupt routes in 2.9 s; eight phases complete; MOSI fails on a preloaded I²C segment |
| 02-mosi-earlier | Move only MOSI to phase −0.5 | Interrupt and MOSI route; SWDIO then fails |
| 03-mosi-after-swd | Move only MOSI to phase 1.5, after SWD | MOSI fails while handling a preloaded SWCLK segment |
| 04-swd-mosi-together | Put MOSI in the SWD phase | Joint phase fails on SWCLK |
| 05-effort-1x | Change only board effort from 10x to 1x | Joint phase fails on SWDIO; no improvement |
| 06-retained | Restore trial 01 and rebuild with --site | Reproduces eight completed phases; MOSI fails on a preloaded I²C SDA segment |

## Retained routing order

Interrupt → charger ground fanout → RF ground fanout → SWD/reset → MCU ground fanout → I²C → supply fanout → remaining ground fanout → MOSI → VDDR → DCDC → charger LP → remaining signals.

The interrupt runs at phase −1, before the existing fanouts. That single ordering change resolves the interrupt using Pipeline 9 in about three seconds. Trial 01 completed eight phases, the best result in this series. The later MOSI-order and grouping changes were not retained. Effort remains 10x; placements and clearances are unchanged.

The `region` declaration is retained from the earlier source, but this installed core does not crop an ordinary first-pass phase to it. The successful interrupt route comes from routing order, without custom code.

Trial artifacts are under `region-experiments/pipeline9-only/`. The published package remains unchanged while raw full-board routing is incomplete.