seveibar/pedometer

ROUTING_EXPERIMENTS.md

> Historical experiment log. The active full-board design now passes raw DRC; see VALIDATION.md and REGIONAL_ROUTING.md. Referenced experiment files are archived outside the package in work/region-board/archived-project-artifacts/.

# Pipeline 9 routing experiments

**Historical report:** the active design now uses Pipeline 9 without custom callbacks. See [PIPELINE9_ONLY.md](PIPELINE9_ONLY.md).

**Follow-up:** [REGION_ROUTING.md](REGION_ROUTING.md) records the newer regional/A* work. The interrupt now routes successfully; twelve phases complete. The following report preserves the earlier seven-phase baseline and its results.

**Zero raw DRC errors was not achieved. This is an unrouted experimental revision, not a fabrication release.**

The source now explicitly selects `beta_pipeline9`, enables HDI vias, and retains seven routing/fanout phases plus the final signal-routing phase. Additions were tested one at a time; unsuccessful interrupt fanouts were removed from the retained design. Component placements and electrical clearance limits were not relaxed.

## Retained sequence

1. Charger GND fanout to inner1.
2. RF shunt capacitor GND fanout to inner1.
3. SWDIO, SWCLK and reset routing using Pipeline 9.
4. MCU GND/exposed-pad fanout to inner1.
5. I²C signal routing using Pipeline 9.
6. 23 SYS_VDD endpoints fanned out to a new inner2 power pour.
7. 40 remaining ground endpoints fanned out to inner1. USB EH3/EH4 and C11 ground retain their existing manual connections.
8. Remaining signal routing using Pipeline 9 — fails.

The first seven phases complete in the final cold-cache run. The final phase has 33 connection groups, down from 73 before the remaining-ground fanout. It fails on the accelerometer interrupt connection in the current run; other experiments failed on SWCLK, I²C, supply or display connections. No completed full-board route was obtained. Successful preliminary phases do not constitute a DRC-clean PCB.

## Validation and reproducibility

- TypeScript and explicit logical net/pin checks pass.
- Raw full-board DRC fails. See `validation.json`; disconnected ports/missing traces are consequences of the aborted full routing transaction.
- No DRC filters, clearance reductions, or post-build via geometry edits are used.
- The previous via-finalization workaround has been removed from `bun run build`. The build exits nonzero on raw DRC errors.
- The current core cache key hashes routing input without the chosen pipeline. `scripts/clear-routing-cache.mjs` clears only generated routing-cache entries before each build, preserving supplier caches. This prevents stale geometry from a different pipeline appearing as Pipeline 9 success.
- Logs confirm Pipeline 9 execution through its solver failure messages. Each fanout/phase has its actual connection counts and SRJ input/output captured.

The original manual paths omitted explicit wire points around layer changes. Adding those points fixed the Pipeline 9 preloaded-trace reconstruction failure and exposed two real PMID/via overlaps. The PMID detour removes those overlaps. The RF ground bridge was replaced by its own plane fanout. These changes are in the TSX source rather than a post-build JSON patch.

## Reproduce

```sh
bun install --frozen-lockfile
bun run typecheck
bun run build -- --autorouter-debug --autorouter-dump-srj all --autorouter-timeout 120s
```

The last command currently returns failure. `dist/index/circuit.json` is the raw, incomplete circuit. `last-completed-phase.png` is a diagnostic image of the last successful phase, not manufacturing artwork. `routing-experiments.json` provides hashes and exact phase errors; the directories below contain source snapshots, raw circuit JSON, validation results and routing diagnostics.

## Incremental runs

| Run/source snapshot | Only the stated phase/configuration/path change was introduced at this step | Raw error records |
|---|---|---:|
| [00-baseline](routing-experiments/00-baseline/index.circuit.tsx) | Cached control: explicit Pipeline 9 property reused prior router cache; not valid evidence. | 4 |
| [00-uncached](routing-experiments/00-uncached/index.circuit.tsx) | Cold-cache Pipeline 9 baseline. | 149 |
| [01-charger-ground](routing-experiments/01-charger-ground/index.circuit.tsx) | Added one charger GND fanout to inner1. | 149 |
| [02-swd-first](routing-experiments/02-swd-first/index.circuit.tsx) | Added SWD/reset phase before remaining nets. | 149 |
| [03-manual-segments](routing-experiments/03-manual-segments/index.circuit.tsx) | Added explicit wire endpoints around existing manual via transitions. | 151 |
| [04-mcu-ground](routing-experiments/04-mcu-ground/index.circuit.tsx) | Added MCU GND/EP fanout. | 151 |
| [05-sensor-signals](routing-experiments/05-sensor-signals/index.circuit.tsx) | Added sensor/interrupt routing phase. | 151 |
| [06-interrupt-fanout](routing-experiments/06-interrupt-fanout/index.circuit.tsx) | Declared interrupt fanout; diagnostics showed it was not executed. | 151 |
| [07-mcu-interrupt](routing-experiments/07-mcu-interrupt/index.circuit.tsx) | Removed conflicting interrupt-net phase assignment and targeted only MCU endpoint; signal fanout still did not execute. | 151 |
| [08-interrupt-endpoints](routing-experiments/08-interrupt-endpoints/index.circuit.tsx) | Expressed interrupt as an explicit endpoint-to-endpoint trace; fanout executed and failed. | 152 |
| [09-interrupt-padding](routing-experiments/09-interrupt-padding/index.circuit.tsx) | Increased interrupt boundary from 0.5 to 2 mm. | 152 |
| [10-interrupt-first](routing-experiments/10-interrupt-first/index.circuit.tsx) | Moved interrupt fanout ahead of SWD. | 152 |
| [11-hdi-enabled](routing-experiments/11-hdi-enabled/index.circuit.tsx) | Explicitly enabled blind/buried vias; verified true in SRJ. | 152 |
| [12-inner-escape](routing-experiments/12-inner-escape/index.circuit.tsx) | Allowed inner2 for interrupt escape. | 152 |
| [13-rf-ground](routing-experiments/13-rf-ground/index.circuit.tsx) | Added RF-shunt ground fanout, replacing manual RF ground bridge. | 154 |
| [14-retained-phases](routing-experiments/14-retained-phases/index.circuit.tsx) | Removed failed interrupt fanout; first five phases completed. | 154 |
| [15-pmid-detour](routing-experiments/15-pmid-detour/index.circuit.tsx) | Detoured existing manual PMID trace around two charger vias; removed two raw overlap errors. | 152 |
| [16-supply-fanout](routing-experiments/16-supply-fanout/index.circuit.tsx) | Added 23-endpoint SYS_VDD fanout and inner2 power pour. | 152 |
| [17-ground-fanout](routing-experiments/17-ground-fanout/index.circuit.tsx) | Added remaining 43 ground endpoints; 40 routed. | 152 |
| [18-ground-without-existing-vias](routing-experiments/18-ground-without-existing-vias/index.circuit.tsx) | Excluded three already-manually-connected ground pads; all seven preliminary phases completed. | 152 |
| [19-directed-interrupt](routing-experiments/19-directed-interrupt/index.circuit.tsx) | Tested a named IRQ bus with a directed right-side fanout; still failed. | 152 |
| [20-final-verification](routing-experiments/20-final-verification/index.circuit.tsx) | Retained successful seven phases; named final signal phase; cold-cache raw validation, no finalizer. | 152 |

Do not interpret error totals across aborted runs as a count of physical shorts: most are missing-connection reports after the router aborts. The meaningful comparison is how far the actual phase sequence completed and which solver/connection failed.

The previous published v0.3.0 package has not been overwritten with this experimental revision. A separate `pedometer-rev-c-reference.zip` preserves that prior local deliverable, including its earlier limitations. It is not a substitute for a completed Pipeline 9 route.