seveibar/am3352-ram-dogbone-and-single-layer-route-test
AM3352BZCZ100 processor connected to a W631GG6MB-12 DDR3 memory chip through a routed, length-matched 16-bit DDR interface with clock/data-strobe pairs and control/address signals.
- Version
- 0.0.9
- License
- unset
- Stars
- 0
Files in (root)/validation
- safe-candidate
- build.log
- copper-audit.json
- coupled-routing.png
- native-drc.json
- pair-coupling.json
- published-verification.json
- README.md
- rounded-comparison.png
- rounded-score.json
- route-comparison.json
- route-efficiency.json
- route-shape.json
- route-turns.json
- routing-input.json
- routing-layers.png
- smoothing-comparison.png
- smoothing-score.json
- summary.json
- tests.log
- turn-comparison.json
