seveibar/am3352-ram-dogbone-and-single-layer-route-test

AM3352BZCZ100 processor connected to a W631GG6MB-12 DDR3 memory chip through a routed, length-matched 16-bit DDR interface with clock/data-strobe pairs and control/address signals.

Version: 0.0.9
License: unset
Stars: 0

validation/summary.json

{
  "status": "PASS",
  "circuitSha256": "3b5adb43b5b6da781cf1b4bf6494b471f759b11a780b7e1cef2251cbb2add3bb",
  "nativeDrcErrors": 0,
  "signals": 47,
  "dogboneVias": 94,
  "signalRoutingVias": 0,
  "simpleCenterlines": true,
  "groups": [
    {
      "name": "DDR_BYTE0",
      "layer": "inner1",
      "signals": 11,
      "minimumPlanarLengthMm": 43.79564411206926,
      "maximumPlanarLengthMm": 43.95820053876962,
      "skewMm": 0.16255642670035542,
      "limitMm": 0.635
    },
    {
      "name": "DDR_BYTE1",
      "layer": "inner2",
      "signals": 11,
      "minimumPlanarLengthMm": 36.921035434315876,
      "maximumPlanarLengthMm": 37.1555758943421,
      "skewMm": 0.2345404600262242,
      "limitMm": 0.635
    },
    {
      "name": "DDR_DQS_PAIR0",
      "layer": "inner1",
      "signals": 2,
      "minimumPlanarLengthMm": 43.87274194508558,
      "maximumPlanarLengthMm": 43.95820053876962,
      "skewMm": 0.08545859368403796,
      "limitMm": 0.127
    },
    {
      "name": "DDR_DQS_PAIR1",
      "layer": "inner2",
      "signals": 2,
      "minimumPlanarLengthMm": 37.133048044119164,
      "maximumPlanarLengthMm": 37.153724760935965,
      "skewMm": 0.020676716816801388,
      "limitMm": 0.127
    },
    {
      "name": "DDR_CK_PAIR",
      "layer": "bottom",
      "signals": 2,
      "minimumPlanarLengthMm": 26.83043925182038,
      "maximumPlanarLengthMm": 26.857614463749087,
      "skewMm": 0.0271752119287072,
      "limitMm": 0.127
    }
  ],
  "scope": "47 DDR signals only; power/reference/ground omitted. Pair skew checked here; measured spacing and bounded pin escapes checked independently in pair-coupling.json."
}