seveibar/am3352-ram-dogbone-and-single-layer-route-test
AM3352BZCZ100 processor connected to a W631GG6MB-12 DDR3 memory chip through a routed, length-matched 16-bit DDR interface with clock/data-strobe pairs and control/address signals.
- Version
- 0.0.9
- License
- unset
- Stars
- 0
validation/pair-coupling.json
{
"status": "PASS",
"method": "Bidirectional nearest-centerline sampling; edge gap subtracts half of each trace width. Copper audit independently checks continuous clearance.",
"sampleStepMm": 0.01,
"endpointEscapeBudgetMm": 6.2,
"mainGapBandMm": [
0.1,
0.155
],
"pairs": [
{
"name": "DDR_DQS_PAIR0",
"planarSkewMm": 0.08545859368398112,
"maxSkewMm": 0.127,
"members": [
{
"sourceTraceId": "source_trace_15",
"signalLengthMm": 42.82541459252912,
"mainMinEdgeGapMm": 0.11979060872795491,
"mainMaxEdgeGapMm": 0.13774273199027093,
"mainP95EdgeGapMm": 0.1200000000071541,
"wholeRouteMaxEdgeGapMm": 0.7910205078273909,
"fractionWithinGapBand": 0.8167600373482726,
"startEscapeExtentMm": 4.929472191014909,
"endEscapeExtentMm": 6.059351212484856,
"interiorViolatingSamples": 0
},
{
"sourceTraceId": "source_trace_16",
"signalLengthMm": 42.73995599884508,
"mainMinEdgeGapMm": 0.1197906087264782,
"mainMaxEdgeGapMm": 0.1380969745396472,
"mainP95EdgeGapMm": 0.12000000000902755,
"wholeRouteMaxEdgeGapMm": 0.8647172951156329,
"fractionWithinGapBand": 0.8336842105263158,
"startEscapeExtentMm": 5.199994646560469,
"endEscapeExtentMm": 5.219994625970315,
"interiorViolatingSamples": 0
}
],
"status": "PASS"
},
{
"name": "DDR_DQS_PAIR1",
"planarSkewMm": 0.0206767168168156,
"maxSkewMm": 0.127,
"members": [
{
"sourceTraceId": "source_trace_27",
"signalLengthMm": 36.020938814695455,
"mainMinEdgeGapMm": 0.11979060871029781,
"mainMaxEdgeGapMm": 0.1375472657491719,
"mainP95EdgeGapMm": 0.12000000001399605,
"wholeRouteMaxEdgeGapMm": 0.6229939208156402,
"fractionWithinGapBand": 0.8632075471698113,
"startEscapeExtentMm": 4.528860750223991,
"endEscapeExtentMm": 0.3799044337936266,
"interiorViolatingSamples": 0
},
{
"sourceTraceId": "source_trace_26",
"signalLengthMm": 36.00026209787867,
"mainMinEdgeGapMm": 0.11979060871189362,
"mainMaxEdgeGapMm": 0.1380227535777978,
"mainP95EdgeGapMm": 0.12000000000783101,
"wholeRouteMaxEdgeGapMm": 1.2379729200610874,
"fractionWithinGapBand": 0.8406440866185453,
"startEscapeExtentMm": 4.608753353824512,
"endEscapeExtentMm": 1.1096998313980961,
"interiorViolatingSamples": 0
}
],
"status": "PASS"
},
{
"name": "DDR_CK_PAIR",
"planarSkewMm": 0.0271752119287072,
"maxSkewMm": 0.127,
"members": [
{
"sourceTraceId": "source_trace_32",
"signalLengthMm": 25.697653305579877,
"mainMinEdgeGapMm": 0.11999999999999614,
"mainMaxEdgeGapMm": 0.13792603740047868,
"mainP95EdgeGapMm": 0.12000000000000019,
"wholeRouteMaxEdgeGapMm": 0.7021649748143708,
"fractionWithinGapBand": 0.8833138856476079,
"startEscapeExtentMm": 4.819559880657393,
"endEscapeExtentMm": 1.2798831218343274,
"interiorViolatingSamples": 0
},
{
"sourceTraceId": "source_trace_33",
"signalLengthMm": 25.724828517508577,
"mainMinEdgeGapMm": 0.11999999999999617,
"mainMaxEdgeGapMm": 0.13736199457354825,
"mainP95EdgeGapMm": 0.12000000000000019,
"wholeRouteMaxEdgeGapMm": 0.6999084844667967,
"fractionWithinGapBand": 0.8935508935508936,
"startEscapeExtentMm": 4.7790392659809955,
"endEscapeExtentMm": 1.2597467521205132,
"interiorViolatingSamples": 0
}
],
"status": "PASS"
}
],
"circuitSha256": "3b5adb43b5b6da781cf1b4bf6494b471f759b11a780b7e1cef2251cbb2add3bb"
}