seveibar/am3352-ram-dogbone-and-single-layer-route-test
AM3352BZCZ100 processor connected to a W631GG6MB-12 DDR3 memory chip through a routed, length-matched 16-bit DDR interface with clock/data-strobe pairs and control/address signals.
- Version
- 0.0.9
- License
- unset
- Stars
- 0
validation/README.md
Current acceptance reports: summary.json, native-drc.json, copper-audit.json, route-shape.json, pair-coupling.json route-efficiency.json and route-turns.json. Each records the SHA-256 of dist/index/circuit.json. route-comparison.json records the comparison with v0.0.6, including placement and scoring changes. turn-comparison.json compares ordinary turns and short jogs against v0.0.8. coupled-routing.png renders the current geometry. Other reports and safe-candidate/ are historical experiments.