seveibar/am3352-ram-dogbone-and-single-layer-route-test

AM3352BZCZ100 processor connected to a W631GG6MB-12 DDR3 memory chip through a routed, length-matched 16-bit DDR interface with clock/data-strobe pairs and control/address signals.

Version: 0.0.9
License: unset
Stars: 0

validation/route-shape.json

{
  "netsWithSelfContact": 0,
  "netsWithSelfClearanceViolations": 0,
  "selfSpacing": [],
  "sharpCornerCount": 0,
  "sharpCorners": [],
  "undersizedCurveVertexCount": 0,
  "undersizedCurves": [],
  "nonOctilinearLongSegmentCount": 0,
  "nonOctilinearLongSegments": [],
  "circuitSha256": "3b5adb43b5b6da781cf1b4bf6494b471f759b11a780b7e1cef2251cbb2add3bb",
  "status": "PASS"
}