seveibar/am3352-ram-dogbone-and-single-layer-route-test

AM3352BZCZ100 processor connected to a W631GG6MB-12 DDR3 memory chip through a routed, length-matched 16-bit DDR interface with clock/data-strobe pairs and control/address signals.

Version: 0.0.9
License: unset
Stars: 0

validation/smoothing-score.json

{
  "criteriaVersion": 1,
  "before": {
    "penalty": 15745.595663301448,
    "bends": 2777,
    "shortSegments": 2202,
    "non45Length": 65.72978316507239,
    "sharpBends": 1417,
    "rapidReversals": 1472,
    "totalLength": 1083.5056760895939
  },
  "after": {
    "penalty": 6020.627679507412,
    "bends": 1311,
    "shortSegments": 672,
    "non45Length": 26.331383975370564,
    "sharpBends": 776,
    "rapidReversals": 429,
    "totalLength": 1083.4994719166739
  },
  "penaltyReductionPercent": 61.76309992806559,
  "maximumLengthChangeMm": 0.003607042762940438,
  "preservedSignals": 47,
  "preservedDogboneVias": 94,
  "newRoutingVias": 0
}