seveibar/am3352-ram-dogbone-and-single-layer-route-test

AM3352BZCZ100 processor connected to a W631GG6MB-12 DDR3 memory chip through a routed, length-matched 16-bit DDR interface with clock/data-strobe pairs and control/address signals.

Version: 0.0.9
License: unset
Stars: 0

validation/route-comparison.json

{
  "circuitSha256": "3b5adb43b5b6da781cf1b4bf6494b471f759b11a780b7e1cef2251cbb2add3bb",
  "baselineVersion": "0.0.6",
  "before": {
    "totalPlanarLengthMm": 3948.6601743711526,
    "maxDetourRatio": 15.22187122139925,
    "meanDetourRatio": 6.970951409595102
  },
  "after": {
    "totalPlanarLengthMm": 1696.5259325688312,
    "maxDetourRatio": 2.5362258067619656,
    "meanDetourRatio": 1.7225064086995059
  },
  "totalCopperReductionPercent": 57.035402955661716,
  "placementChange": {
    "ramYBeforeMm": -19,
    "ramYAfterMm": -27,
    "boardBeforeMm": [
      70,
      60
    ],
    "boardAfterMm": [
      70,
      70
    ]
  },
  "scoringChange": {
    "pinEscapeBudgetBeforeMm": 4.5,
    "pinEscapeBudgetAfterMm": 6.2,
    "mainGapBandMm": [
      0.1,
      0.155
    ],
    "skewLimitsUnchanged": true
  }
}