seveibar/am3352-ram-dogbone-and-single-layer-route-test

AM3352BZCZ100 processor connected to a W631GG6MB-12 DDR3 memory chip through a routed, length-matched 16-bit DDR interface with clock/data-strobe pairs and control/address signals.

Version: 0.0.9
License: unset
Stars: 0

validation/turn-comparison.json

{
  "circuitSha256": "3b5adb43b5b6da781cf1b4bf6494b471f759b11a780b7e1cef2251cbb2add3bb",
  "baselineVersion": "0.0.8",
  "ordinaryTurnsBefore": 1830,
  "ordinaryTurnsAfter": 888,
  "ordinaryTurnReductionPercent": 51.47540983606558,
  "shortJogsBefore": 1116,
  "shortJogsAfter": 451,
  "shortJogReductionPercent": 59.587813620071685,
  "maximumPlanarLengthChangeMm": 1.0129497240995988e-10,
  "placementAndOutlineUnchanged": true,
  "allExistingLimitsUnchanged": true,
  "differentialPairGeometryRetained": true
}