seveibar/am3352-ram-dogbone-and-single-layer-route-test

AM3352BZCZ100 processor connected to a W631GG6MB-12 DDR3 memory chip through a routed, length-matched 16-bit DDR interface with clock/data-strobe pairs and control/address signals.

Version: 0.0.9
License: unset
Stars: 0

validation/tests.log

bun test v1.3.2 (b131639c)

scripts/coupled-plan.test.ts:
(pass) all 47 paths have two endpoint vias and pass retained skew limits [10.42ms]
(pass) a changed placement cannot silently reuse the geometric plan [4.95ms]
(pass) changed width and board bounds require replanning [3.68ms]
(pass) ordinary-turn cleanup preserves every tuned trace length [6.76ms]
(pass) turn cleanup retains both members of every differential pair [2.72ms]

 5 pass
 0 fail
 104 expect() calls
Ran 5 tests across 1 file. [102.00ms]
PASS: pair separation fails independently of passing length skew
PASS: straight and 45 degree tracks, real-radius arcs, undersized arcs, sharp corners, oblique lines, and sampling-invariant self contact
PASS: stair-step turns, length-preserving replacement, short jogs, collinear points and curved-meander exclusion