seveibar/am3352-ram-dogbone-and-single-layer-route-test

AM3352BZCZ100 processor connected to a W631GG6MB-12 DDR3 memory chip through a routed, length-matched 16-bit DDR interface with clock/data-strobe pairs and control/address signals.

Version: 0.0.9
License: unset
Stars: 0

validation/rounded-score.json

{
  "criteriaVersion": 2,
  "before": {
    "maximumHeadingChangeDeg": 178.25048520403575,
    "cornersOver45Deg": 791,
    "acuteInteriorCorners": 194
  },
  "after": {
    "maximumHeadingChangeDeg": 5.0000000570474485,
    "cornersOver45Deg": 0,
    "acuteInteriorCorners": 0
  },
  "signals": 47,
  "preservedDogboneVias": 94,
  "addedVias": 0,
  "minimumRadiusGuaranteed": false
}