AM3352BZCZ100 processor connected to a W631GG6MB-12 DDR3 memory chip through a routed, length-matched 16-bit DDR interface with clock/data-strobe pairs and control/address signals.
# AM3352 / RAM: compact, coupled single-layer routing test
All **47/47 DDR signals** are routed with **94 dogbone vias and zero routing vias**. Native DRC, independent copper clearance, same-net spacing, angle/radius, timing and measured pair-coupling checks pass.
The long external tuning loops have been replaced by compact ordered lanes with rounded meanders. Total planar copper length fell **57%**, from 3948.66 mm to **1696.53 mm**. Worst length/direct-distance ratio fell from **15.22× to 2.54×**, and the average from **6.97× to 1.72×**. Both endpoint stubs are included.
| Group | Planar length | Skew | Limit |
| --- | --- | --- | --- |
| Byte 0 (11 signals, inner1) | 43.80–43.96 mm | 0.163 mm | 0.635 mm |
| Byte 1 (11 signals, inner2) | 36.92–37.16 mm | 0.235 mm | 0.635 mm |
| DQS0 | 43.87–43.96 mm | 0.085 mm | 0.127 mm |
| DQS1 | 37.13–37.15 mm | 0.021 mm | 0.127 mm |
| Clock (bottom) | 26.83–26.86 mm | 0.027 mm | 0.127 mm |
**Placement changed:** U1 remains at (0, 0); U3 moved 8 mm down, from y = −19 to y = −27, to provide tuning space. The outline is now **70 × 70 mm**, four layers, 1.2 mm thick. The original TSX buses, differential pairs and their skew limits remain declared.
## Ordinary-turn cleanup
A final post-processing phase reduces **ordinary direction turns from 1830 to 888 (51%)**, and **jogs shorter than 0.25 mm from 1116 to 451 (60%)**. Curved meander segments are excluded from these counts. Both the tuning curves and differential-pair geometry are retained, protecting coupling at the pins as well as along the main run. Each replacement has the same length as the original octilinear run, so every signal keeps its tuned length. Continuous copper/self clearance and bidirectional pair proximity gate the replacements.
The offline generator is `scripts/simplify-ordinary-turns.py INPUT OUTPUT`; run all independent audits after generating a candidate. The custom final `ordinaryTurnCleanup` phase evaluates the generated primitives and rechecks timing. `validation/route-turns.json` and `turn-comparison.json` contain the measured counts and per-net results against v0.0.8.
## Pair geometry and scoring
DQS tuning uses shared centerlines and analytic offset arcs. Ordinary tracks are horizontal, vertical or 45°; intentional tuning curves have at least 0.12 mm centerline radius. No sharp corners, self contacts or nonlocal self-clearance failures remain.
The main paired runs have measured edge gaps **0.120–0.138 mm**, within the unchanged 0.10–0.155 mm band. Pin-escape exceptions are now bounded to the first/last **6.2 mm**, increased from 4.5 mm to accommodate the compact escapes and local skew corrections. The worst measured escape extent is **6.06 mm**. This is an explicit scoring change: it does not imply that the whole trace is coupled. Depending on the member, **81.7–89.4%** of the complete signal-layer path lies inside the main gap band. Full-route maximum gaps and both escape extents are reported in `validation/pair-coupling.json`.
Route efficiency is now a hard acceptance gate: worst detour ≤3.5× and mean detour ≤2.3×. See [acceptance criteria](design/coupled-routing-criteria.md). All reports include the exact built circuit's SHA-256.
## Custom phases
1. `dogboneFanout` generates local top-layer diagonal escapes to 0.3/0.15 mm vias at both packages.
2. `singleLayerRoute` materializes the board-specific guides, with each byte on one signal layer.
3. `coupledTuning` materializes the optimized straight/curved paths and verifies bus/pair skew.
4. `ordinaryTurnCleanup` replaces unnecessary octilinear jogs with the generated equal-length paths and verifies timing again.
`routing/coupled-route-plan.json` is a **generated geometric plan**, not a generic autorouter. Rebuilding evaluates its stored primitives; it does not repeat the offline search. Runtime guards reject changed endpoints, trace width or board bounds. Geometry, footprints or topology changes require replanning and all audits. Address/control layer assignments are read from the same plan as the dogbones.
## Reproduce and verify
Use tscircuit 0.0.2646 and Python with NumPy and Shapely:
```sh
tsci build index.circuit.tsx --disable-parts-engine --autorouter-dump-srj all --pcb-svgs
python scripts/compact-dist.py
python scripts/validate-routing.py
AUDIT_REPORT_PATH=validation/copper-audit.json python scripts/audit-copper.py --strict
python scripts/audit-route-shape.py dist/index/circuit.json --strict > validation/route-shape.json
python scripts/audit-pair-coupling.py
python scripts/audit-route-efficiency.py > validation/route-efficiency.json
python scripts/audit-route-turns.py > validation/route-turns.json
bun test scripts/coupled-plan.test.ts
python scripts/test-pair-coupling.py
python scripts/test-route-shape-audit.py
python scripts/test-route-turns.py
```
Current reports are `summary.json`, `copper-audit.json`, `route-shape.json`, `pair-coupling.json`, `route-efficiency.json`, `native-drc.json`, and `route-turns.json`. Earlier smoothing reports are historical.
This remains the requested **47-signal routing experiment**: power, ground and reference nets are omitted. Geometric DRC and length matching are not a DDR signal-integrity signoff.