seveibar/am3352-ram-dogbone-and-single-layer-route-test

AM3352BZCZ100 processor connected to a W631GG6MB-12 DDR3 memory chip through a routed, length-matched 16-bit DDR interface with clock/data-strobe pairs and control/address signals.

Version: 0.0.9
License: unset
Stars: 0

package.json

{
  "name": "@tsci/seveibar.am3352-ram-dogbone-and-single-layer-route-test",
  "version": "0.0.9",
  "description": "AM3352 / DDR3: custom dogbone fanout, no-via single-layer bus routing, and length matching",
  "main": "index.circuit.tsx",
  "scripts": {
    "build": "tsci build index.circuit.tsx --disable-parts-engine --autorouter-dump-srj all --pcb-svgs"
  },
  "devDependencies": {
    "tscircuit": "0.0.2646",
    "@types/react": "^19.3.0",
    "typescript": "^5.0.0"
  }
}