seveibar/am3352-ram-dogbone-and-single-layer-route-test
AM3352BZCZ100 processor connected to a W631GG6MB-12 DDR3 memory chip through a routed, length-matched 16-bit DDR interface with clock/data-strobe pairs and control/address signals.
- Version
- 0.0.9
- License
- unset
- Stars
- 0
Files in (root)/scripts
- __pycache__
- audit-copper.py
- audit-pair-coupling.py
- audit-route-efficiency.py
- audit-route-shape.py
- audit-route-turns.py
- compact-dist.py
- coupled-plan.test.ts
- score-smoothing.ts
- simplify-ordinary-turns.py
- test-pair-coupling.py
- test-route-shape-audit.py
- test-route-turns.py
- validate-rounded.py
- validate-routing.py