README.md
# CM5 Minimal Carrier — V1 / revision B
A **64 × 60 mm, four-layer tsCircuit carrier** with USB-C power and one full-size HDMI Type-A output. It contains 15 fitted parts, including the two CM5 sockets, plus six bare bottom-side probe pads. No Ethernet, GPIO headers, USB data ports, SD, PCIe, LEDs, buttons, fan or other peripherals are added.
**Status: fully routed engineering prototype, with automated electrical and copper checks. Not released for fabrication.** The current results are in `output/validation.json` and `output/drc.json`. Complete the open items in [the fabrication checklist](https://tscircuit.com/pixalynx/cm5-minimal-carrier/blob/docs/fabrication-checklist.md) before placing an order. A clean DRC does not verify impedance, USB-C inrush, connector current rating, or real HDMI performance.
Revision B incorporates the [CM5 MINIMA comparison](https://tscircuit.com/pixalynx/cm5-minimal-carrier/blob/docs/minima-comparison.md), corrected manufacturing origins, JLC-calculated HDMI geometry and export-level checks. [JLC review notes](https://tscircuit.com/pixalynx/cm5-minimal-carrier/blob/docs/jlcpcb-order-notes.md) record the outstanding order decisions.
The part-import review replaces D1/U1 preview bodies with exact catalogue imports from `tsci search`/`tsci import` and fixes OBJ material colours across the carrier. Both electrical components were already present; all 1,221 PCB records remain identical. See [import notes](https://tscircuit.com/pixalynx/cm5-minimal-carrier/blob/imports/README.md).
## Open the design
- [Visual review: PCB layers, all schematic sheets and BOM](https://tscircuit.com/pixalynx/cm5-minimal-carrier/blob/output/review.html)
- [Populated carrier 3D render](https://tscircuit.com/pixalynx/cm5-minimal-carrier/blob/output/assembly-3d.png). The tsCircuit **3D** tab includes all 15 carrier component bodies **plus the seated CM5 module**. The static render and KiCad viewer remain carrier-only. Refresh/rebuild an older loaded tsCircuit view. [Model sources and limitations](https://tscircuit.com/pixalynx/cm5-minimal-carrier/blob/models/README.md).
- [Top copper](https://tscircuit.com/pixalynx/cm5-minimal-carrier/blob/output/pcb-top.svg), [ground plane](https://tscircuit.com/pixalynx/cm5-minimal-carrier/blob/output/pcb-inner1.svg), [5 V plane](https://tscircuit.com/pixalynx/cm5-minimal-carrier/blob/output/pcb-inner2.svg), [bottom copper](https://tscircuit.com/pixalynx/cm5-minimal-carrier/blob/output/pcb-bottom.svg)
- [Assembly drawings and pad-1/placement review](https://tscircuit.com/pixalynx/cm5-minimal-carrier/blob/output/assembly-review.html)
- [CAM consistency audit and hashes](https://tscircuit.com/pixalynx/cm5-minimal-carrier/blob/output/manufacturing-audit.json), [revision B manufacturing review bundle](https://tscircuit.com/pixalynx/cm5-minimal-carrier/blob/output/cm5-minimal-revB-manufacturing-review.zip)
- [Complete BOM](https://tscircuit.com/pixalynx/cm5-minimal-carrier/blob/output/bom.csv), [JLCPCB BOM](https://tscircuit.com/pixalynx/cm5-minimal-carrier/blob/output/jlcpcb-bom.csv), [CPL for placement review](https://tscircuit.com/pixalynx/cm5-minimal-carrier/blob/output/jlcpcb-cpl-REVIEW.csv)
- [All 200 CM5 pins](https://tscircuit.com/pixalynx/cm5-minimal-carrier/blob/output/cm5-pin-audit.csv), [named-net list](https://tscircuit.com/pixalynx/cm5-minimal-carrier/blob/output/netlist.json)
- [Schematic sheets](https://tscircuit.com/pixalynx/cm5-minimal-carrier/blob/output/schematics), [independent KiCad PCB export](https://tscircuit.com/pixalynx/cm5-minimal-carrier/blob/output/cm5-minimal.kicad_pcb)
- Review-only Gerber/drill files: `output/fabrication-REVIEW/`. These are **not a fabrication release**.
```sh
bun install --frozen-lockfile
bun run dev # http://localhost:3905
bun run build # regenerate, typecheck, build, DRC, validate, render, export
bun run check # check the existing build
```
Bun and KiCad 10 with Python `pcbnew` are needed for the complete build. The build finds the installed macOS KiCad automatically. Elsewhere, set `KICAD_CLI` and `KICAD_PYTHON`; install Poppler only if re-extracting the reference PDF. `lib/footprints.json` contains all necessary geometry, so normal builds do not depend on global footprint libraries or sibling projects. Dependencies are pinned in `bun.lock`. The tsCircuit version is 0.0.2462.
## Block diagram
```text
USB-C J3 ────── 5 V plane ────── J1 / CM5 ── HDMI0 ── ESD ── HDMI J4 ── TV
│ │
└── CC1/CC2 ─────┤ CM5's internal USB-PD controller
└── RT9742 current-limited switch ── HDMI +5 V
```
## Module and boot assumptions
Use a **non-wireless eMMC CM5**, for example Raspberry Pi **CM5004016 / SC1564** (4 GB RAM, 16 GB eMMC). Program Raspberry Pi OS and configure automatic boot/HDMI on a separate CM5 IO board before installation. This carrier has no way to flash a blank eMMC module in place. A CM5 Lite will not have a local boot medium on this board.
The four-layer copper extends under the module. This revision deliberately assumes the non-wireless SKU; it does **not** provide the PCB antenna keepout needed by an onboard-antenna wireless CM5. Do not substitute that SKU without revising the copper/mechanics or qualifying the external-antenna arrangement.
CM5 generates its own 3.3 V and 1.8 V rails. Carrier pin 78 (GPIO_VREF) is connected to its 3.3 V outputs at 84 and 86, with local decoupling. The 1.8 V outputs are unused. nRPIBOOT, PMIC_Enable, PWR_Button, EEPROM_nWP, SD_VDD_OVERRIDE, wireless-disable and other unused signals are explicitly left NC according to their documented defaults. Cold power application boots the module. After software power-off, cycle USB-C power to restart. There is no RTC battery.
A passive heatsink/thermal solution is a separate mechanical item and must be qualified for the workload. No fan connector has been added.
## Connector geometry
Both Amphenol **10164227-1001A1RLF** sockets are the CM5-compatible 100-contact, 0.4 mm pitch, 1.5 mm stacking-height parts specified by Raspberry Pi. The pad coordinates come from the official CM5IO revision 2 KiCad footprint, rather than a CM4 substitute.
Coordinates below are millimetres, viewed from above the carrier, +Y upward:
| Item | Position / dimensions |
|---|---|
| Carrier outline | X −32…+32, Y −30…+30 |
| CM5 outline | Centre (−10, 0), 40 × 55 mm |
| J1 centre | (−27, −2.5), rotation 0° |
| J2 centre | (+7, −2.5), rotation 0° |
| Socket centre spacing | 34.000 mm |
| J1 pad 1 | (−28.54, +7.30) |
| J2 pad 1 / official pin 101 | (+5.46, +7.30) |
| Mounting holes | (−26.5, ±24), (+6.5, ±24), Ø2.7 mm NPTH |
| Hole spacing | 33 × 48 mm; 3.5 mm inset on the module |
**J1 contacts 1–100 are CM5 pins 1–100. J2 contacts 1–100 are CM5 pins 101–200.** This local numbering allows each physical socket to have its actual 1–100 contact numbering. The complete crosswalk is in `output/cm5-pin-audit.csv`.
The USB-C and HDMI connectors both face the right edge, with space between them for plugs. Their lead-in, peg, shield-slot and signal-pad geometry is extracted from the official IO board. Keep the CM5 area free of top-side components: the 1.5 mm stack option has no usable under-module component clearance. C2, C3 and C6 are on the bottom side. Use mounting hardware that maintains the connector stack height; verify actual module, standoff, heatsink and enclosure fit before ordering.
## Power
See [power architecture](https://tscircuit.com/pixalynx/cm5-minimal-carrier/blob/docs/power.md). Recommended supply: **USB-PD 5 V / 5 A**, such as the official Raspberry Pi 27 W USB-C supply, with a 5 A electronically marked cable. A charger labelled “65 W” does not necessarily offer 5 A at 5 V.
CM5 already contains the PD controller and sink termination. J3 CC1 connects to CM5 pin 94; CC2 connects to 96. **There are no external 5.1 kΩ resistors and no second PD sink.** These would duplicate the module's CC termination. USB data and SBU pins remain unused. The design requests no 9/12/15/20 V profile and contains no buck converter.
## HDMI
See [HDMI and PCB routing](https://tscircuit.com/pixalynx/cm5-minimal-carrier/blob/docs/hdmi-layout.md). All eight TMDS/clock conductors are explicitly routed on L1, with no signal vias. U2/U3 protect the TMDS pairs and U4 protects CEC, DDC and HPD. HDMI pin 18 gets 5 V through the same RT9742SNGV switch used by CM5IO. Ground shields are bonded directly to the ground plane.
The target is **100 Ω differential** using JLCPCB **JLC04161H-3313**, 1.6 mm nominal, 1 oz outer / 0.5 oz inner copper. The routing starts at 0.1234 mm width and 0.2301 mm nominal straight-run edge gap, from JLC’s calculator. The manufacturer must confirm the finished geometry for 100 Ω, including mask and fanout discontinuities. Do not order the default 7628 four-layer stack-up with these dimensions.
## Components and sourcing
All fitted components have verified LCSC catalogue identities. That does not guarantee stock, Basic status, JLC placement-library orientation or assembly availability at order time. Check each row in the JLC quote. Do not silently substitute similarly named ESD devices from another manufacturer.
| References | Manufacturer / MPN | LCSC | Purpose |
|---|---|---|---|
| J1, J2 | Amphenol 10164227-1001A1RLF | C6782225 | Correct CM5 sockets |
| J3 | GCT USB4105-GF-A | C3020560 | USB-C power, 5 A aggregate VBUS rating |
| J4 | EDAC 690-019-298-412 | C5291558 | HDMI Type-A |
| U1 | Richtek RT9742SNGV | C3235509 | 0.5 A HDMI supply switch |
| U2–U4 | Texas Instruments TPD4E05U06DQAR | C138714 | Low-capacitance ESD protection |
| D1 | Diodes Inc. SMAJ5.0A-13-F | C87074 | VBUS transient suppression |
| C1, C5 | Samsung CL21A106KAYNNNE | C15850 | 10 µF, 25 V, X5R, 0805 |
| C2 | Murata GRM31CR61A476KE15L | C426659 | 47 µF, 10 V, X5R, 1206 bulk |
| C3, C6 | Samsung CL05B104KO5NNNC | C1525 | 100 nF, 16 V, X7R, 0402 |
| C4 | Samsung CL21B105KBFNNNE | C28323 | 1 µF, 50 V, X7R, 0805 |
Manual/system sourcing: the CM5, a compatible PSU/cable, HDMI cable, four appropriate M2.5 supports/fasteners, and passive thermal hardware. J1/J2 and J4 may require JLC global sourcing or manual installation if assembly stock is unavailable. The PCB uses two-sided assembly because of the module's height clearance. The mixed SMT/through-hole shield stakes require the assembler to confirm its soldering process.
## Validation and remaining warnings
The build checks all 200 official pin names, the exact split footprint geometry, every intended emitted pin-to-net connection, power/configuration pins, CC wiring, USB data NCs, TVS polarity, HDMI mapping, pair lengths and zero signal vias. A separate export of the emitted copper is filled and checked in KiCad with **no DRC exclusions**. The exporter uses standard plated through-vias on all four layers; it does not request blind or buried vias.
The passive ESD arrays legitimately have no supply pin. tsCircuit's generic chip checker therefore emits `source_no_power_pin_defined_warning` for U2/U3/U4; those warnings remain in the original circuit JSON and validation report. No dummy power pins have been added to suppress them.
The open items are physical qualification, not waived DRC errors: impedance and high-speed fanouts, USB-PD negotiation/inrush, rail droop, connector thermal/current capacity, ESD robustness, paste/assembly placement, cooler clearance and actual display interoperability. The 5 A supply recommendation is **not** a claim that the six module power contacts have been qualified for 5 A continuous current.
## Files and provenance
`index.circuit.tsx` renders the complete schematic, geometry, traces and planes. `scripts/design.py` defines the electrical intent and placement; `scripts/route.py` generates the explicit routes. `lib/footprints.json` is extracted reference geometry. `scripts/export-kicad.py` exports the emitted circuit JSON for independent checking, with no autorouting. Editing only the generated KiCad board will not update tsCircuit; edit the generators and rebuild.
The reference implementation is the **official CM5IO revision 2**, and the pinout is checked against **CM5 datasheet Release 3, 8 June 2026**. See [sources and review notes](https://tscircuit.com/pixalynx/cm5-minimal-carrier/blob/docs/sources.md). These references do not constitute Raspberry Pi endorsement of this carrier.
