# AM62L32 ↔ LPDDR4 automatic-breakout reproduction
[View the published tscircuit package](https://tscircuit.com/0hmX/am62l-lpddr4-breakout-repro).
This minimal tscircuit project connects exactly 33 direct DDR signals between a
TI AM62L32 (`fccsp_373_anb`) and a Micron MT53E1G16D1ZW LPDDR4 device. Each BGA
is the sole component inside its own sibling `<breakout>`. The traces, buses,
and three differential-pair declarations live at board scope so every signal
crosses both breakout boundaries.
Core automatically creates both sets of breakout points, routes both BGA
fanouts, synchronizes their exits into the parent connections, and then runs the
normal board autorouter through the middle. The byte-1 row groups use shared
`<bus preferredLayer="...">` declarations so every signal exits the SoC and RAM
breakouts on the same PCB layer. The board uses the built-in `beta_pipeline9`
autorouter at the standard `1x` effort level and routes the four byte-1 bus
groups in separate phases so a fresh focused preview completes within the
registry worker timeout. The source contains no manual vias, breakout points,
PCB trace primitives, route coordinates, or custom autorouter algorithm.
## Important limitation
This is a 33-signal routing reproduction only. It intentionally omits all DDR
power, ground, decoupling, reference-voltage, termination, stackup, impedance,
and timing-signoff requirements. It is not a complete DDR design and is not
manufacturable.
## Pinned runtime
- `tscircuit`: `0.0.2358`
- `@tscircuit/core`: `0.0.1707`
- Core git commit / npm `gitHead`: `911a81750403dbc93ddf5d971f952d528a5ec4bd`
- `@tsci/tscircuit.ti`: `1.0.100`
- `@tsci/0hmX.mt53e1g16d1zw-footprint`: `1.0.2`
The exact Core dependency is both direct and overridden in `package.json`; no
machine-specific `file:` dependency is used.
## Commands
```sh
bun install
bun run typecheck
bun run build
bun run snapshot
bun run build:pcb
bun run verify
bunx tsci build ddr-byte1-only.circuit.tsx --pcb-svgs --pcb-png \
--autorouter-debug --autorouter-dump-srj all
bun run verify:byte1-layers
bunx tsci check shorts dist/ddr-byte1-only/circuit.json
```
`build` (and its `build:pcb` alias) enables PCB SVG/PNG generation plus
autorouter phase diagnostics and records wall-clock time in
`dist/routing-timing.json`. `verify` checks the
structural invariants and writes `dist/verification-report.json` while reporting
all routing and clearance errors without hiding an automatic-routing failure.
`verify:byte1-layers` reads the two fanout phase dumps and fails if any byte-1
signal exits the SoC and RAM breakouts on different layers.
See `RESULTS.md` for the attempted configurations and observed outcome.