0hmX/am62l-lpddr4-breakout-repro
This code defines the physical layout, pin assignments, and power connections for the TI AM62L system-on-chip with DDR4/LPDDR4 memory, including detailed component placement, decoupling capacitors, and signal traces for a 6-layer PCB design.
- Version
- 1.0.14
- License
- unset
- Stars
- 0
am62l-soc-dram-6layer.circuit.tsx
PCB
Schematic
import { MT53E1G16D1ZW, ballMap } from "@tsci/0hmX.mt53e1g16d1zw-footprint"
import { AM62L32 } from "@tsci/tscircuit.ti"
import { Fragment } from "react"
import {
ENDPOINT_GROUP_BALLS,
ENDPOINT_SPECS,
FUNCTIONAL_IO_ASSIGNMENTS,
SOC_DDR_DIRECT_BALLS,
SOC_GROUND_BALLS,
SOC_LPDDR4_UNUSED_DDR_BALLS,
SOC_NC_BALLS,
SOC_POWER_BALLS,
type EndpointGroupId,
} from "./am62l-connectivity"
import { DDR_CONNECTIONS } from "./ddr-connections"
const endpointPinLabels = (groupId: EndpointGroupId) => {
const { capacity, ref } = ENDPOINT_SPECS[groupId]
const signals = ENDPOINT_GROUP_BALLS[groupId].map(({ signal }) => signal)
return Object.fromEntries(
Array.from({ length: capacity }, (_, index) => [
`pin${index + 1}`,
signals[index] ?? `UNUSED_${ref}_${index + 1}`,
]),
)
}
const endpointNoConnect = (groupId: EndpointGroupId) => {
const { capacity } = ENDPOINT_SPECS[groupId]
const used = ENDPOINT_GROUP_BALLS[groupId].length
return Array.from(
{ length: capacity - used },
(_, index) => `pin${used + index + 1}`,
)
}
type EndpointProps = {
groupId: EndpointGroupId
label: string
footprint: string
pcbX: number
pcbY: number
pcbRotation?: number
labelX?: number
labelY?: number
}
const FakeChipEndpoint = ({
groupId,
label,
footprint,
pcbX,
pcbY,
pcbRotation = 0,
labelX = pcbX,
labelY = pcbY + 6,
}: EndpointProps) => {
const { ref } = ENDPOINT_SPECS[groupId]
return (
<Fragment>
<chip
name={ref}
manufacturerPartNumber={`PLACEMENT_STUB_${label.replaceAll(" ", "_")}`}
footprint={footprint}
pinLabels={endpointPinLabels(groupId) as any}
noConnect={endpointNoConnect(groupId) as any}
pcbX={pcbX}
pcbY={pcbY}
pcbRotation={pcbRotation}
noSchematicRepresentation
/>
<silkscreentext
text={label}
pcbX={labelX}
pcbY={labelY}
fontSize="0.9mm"
anchorAlignment="center"
/>
</Fragment>
)
}
const FakeHeaderEndpoint = ({
groupId,
label,
pcbX,
pcbY,
pcbRotation = 0,
labelX = pcbX,
labelY = pcbY + 6,
}: Omit<EndpointProps, "footprint">) => {
const { capacity, ref } = ENDPOINT_SPECS[groupId]
return (
<Fragment>
<chip
name={ref}
manufacturerPartNumber={`PLACEMENT_STUB_${label.replaceAll(" ", "_")}`}
footprint={`pinrow${capacity}_p2.54mm_nopinlabels_rows2`}
pinLabels={endpointPinLabels(groupId) as any}
noConnect={endpointNoConnect(groupId) as any}
pcbX={pcbX}
pcbY={pcbY}
pcbRotation={pcbRotation}
noSchematicRepresentation
/>
<silkscreentext
text={label}
pcbX={labelX}
pcbY={labelY}
fontSize="0.9mm"
anchorAlignment="center"
/>
</Fragment>
)
}
type PowerBallTarget = {
component: "U1" | "U2"
ball: string
signal: string
physicalPin: number
}
type AutoPlacedDecouplingCapacitor = {
name: string
capacitance: string
footprint: "cap0201" | "cap0402"
rail: string
region: string
target: PowerBallTarget
}
type FixedBulkCapacitor = {
name: string
capacitance: string
footprint: "cap0603"
pcbX: number
pcbY: number
pcbRotation: number
rail: string
}
// No PCB coordinates or rotations are stored for these parts. pcbPack owns
// their bottom-layer placement and uses the explicit target-ball traces below.
const socAutoPlacedDecoupling: readonly AutoPlacedDecouplingCapacitor[] = [
{ name: "C1", capacitance: "0.1uF", footprint: "cap0201", rail: "VDD_CORE", region: "CORE", target: { component: "U1", ball: "J9", signal: "VDD_CORE1", physicalPin: 142 } },
{ name: "C2", capacitance: "0.1uF", footprint: "cap0201", rail: "VDD_CORE", region: "CORE", target: { component: "U1", ball: "J13", signal: "VDD_CORE3", physicalPin: 144 } },
{ name: "C3", capacitance: "0.1uF", footprint: "cap0201", rail: "VDD_CORE", region: "CORE", target: { component: "U1", ball: "P10", signal: "VDD_CORE10", physicalPin: 219 } },
{ name: "C4", capacitance: "0.1uF", footprint: "cap0201", rail: "VDD_CORE", region: "CORE", target: { component: "U1", ball: "P14", signal: "VDD_CORE12", physicalPin: 221 } },
{ name: "C5", capacitance: "0.1uF", footprint: "cap0201", rail: "VDDS_DDR", region: "DDR", target: { component: "U1", ball: "M7", signal: "VDDS_DDR2", physicalPin: 184 } },
{ name: "C6", capacitance: "0.1uF", footprint: "cap0201", rail: "VDDS_DDR", region: "DDR", target: { component: "U1", ball: "P8", signal: "VDDS_DDR5", physicalPin: 217 } },
{ name: "C7", capacitance: "0.1uF", footprint: "cap0201", rail: "VDDA_PLL1", region: "ANALOG_PLL", target: { component: "U1", ball: "K12", signal: "VDDA_PLL1", physicalPin: 154 } },
{ name: "C8", capacitance: "0.1uF", footprint: "cap0201", rail: "VDDA_DDR_PLL0", region: "DDR_ANALOG_PLL", target: { component: "U1", ball: "M10", signal: "VDDA_DDR_PLL0", physicalPin: 186 } },
{ name: "C9", capacitance: "0.1uF", footprint: "cap0201", rail: "VDDS_IO_1V8", region: "IO", target: { component: "U1", ball: "H8", signal: "VDDSHV2", physicalPin: 127 } },
{ name: "C10", capacitance: "0.1uF", footprint: "cap0201", rail: "VDDS_IO_3V3", region: "IO", target: { component: "U1", ball: "J16", signal: "VDDSHV0_1", physicalPin: 146 } },
{ name: "C11", capacitance: "0.1uF", footprint: "cap0201", rail: "VDDS_WKUP", region: "WAKEUP", target: { component: "U1", ball: "P16", signal: "VDDS_WKUP", physicalPin: 223 } },
{ name: "C12", capacitance: "0.1uF", footprint: "cap0201", rail: "VDD_RTC", region: "RTC", target: { component: "U1", ball: "T17", signal: "VDD_RTC", physicalPin: 248 } },
{ name: "C13", capacitance: "0.1uF", footprint: "cap0201", rail: "VDDS_RTC", region: "RTC", target: { component: "U1", ball: "T18", signal: "VDDS_RTC", physicalPin: 249 } },
{ name: "C14", capacitance: "0.1uF", footprint: "cap0201", rail: "VDDS_OSC0", region: "OSC", target: { component: "U1", ball: "R16", signal: "VDDS_OSC0", physicalPin: 233 } },
{ name: "C15", capacitance: "0.1uF", footprint: "cap0201", rail: "VDD_CORE", region: "CORE", target: { component: "U1", ball: "L15", signal: "VDD_CORE7", physicalPin: 171 } },
{ name: "C16", capacitance: "0.1uF", footprint: "cap0201", rail: "VDD_CORE", region: "CORE", target: { component: "U1", ball: "R9", signal: "VDD_CORE13", physicalPin: 229 } },
{ name: "C17", capacitance: "0.1uF", footprint: "cap0201", rail: "VDDS_DDR", region: "DDR", target: { component: "U1", ball: "L8", signal: "VDDS_DDR1", physicalPin: 167 } },
{ name: "C18", capacitance: "0.1uF", footprint: "cap0201", rail: "VDDS_IO_1V8", region: "IO", target: { component: "U1", ball: "T14", signal: "VDDS0", physicalPin: 246 } },
]
const socBulkDecoupling: readonly FixedBulkCapacitor[] = [
{ name: "C19", capacitance: "10uF", footprint: "cap0603", pcbX: -8, pcbY: -3.5, pcbRotation: 0, rail: "VDD_CORE" },
{ name: "C20", capacitance: "2.2uF", footprint: "cap0603", pcbX: 5.4, pcbY: 8.3, pcbRotation: 90, rail: "VDDS_DDR" },
]
const dramAutoPlacedDecoupling: readonly AutoPlacedDecouplingCapacitor[] = [
{ name: "C23", capacitance: "1uF", footprint: "cap0402", rail: "VDD1", region: "VDD1", target: { component: "U2", ball: "F1", signal: "VDD1_F1", physicalPin: 51 } },
{ name: "C24", capacitance: "0.1uF", footprint: "cap0201", rail: "VDD2", region: "VDD2", target: { component: "U2", ball: "H1", signal: "VDD2_H1", physicalPin: 71 } },
{ name: "C25", capacitance: "0.1uF", footprint: "cap0201", rail: "VDDQ", region: "VDDQ", target: { component: "U2", ball: "D1", signal: "VDDQ_D1", physicalPin: 31 } },
{ name: "C26", capacitance: "1uF", footprint: "cap0402", rail: "VDD1", region: "VDD1", target: { component: "U2", ball: "F12", signal: "VDD1_F12", physicalPin: 60 } },
{ name: "C27", capacitance: "0.1uF", footprint: "cap0201", rail: "VDD2", region: "VDD2", target: { component: "U2", ball: "H12", signal: "VDD2_H12", physicalPin: 80 } },
{ name: "C28", capacitance: "0.1uF", footprint: "cap0201", rail: "VDDQ", region: "VDDQ", target: { component: "U2", ball: "D12", signal: "VDDQ_D12", physicalPin: 40 } },
{ name: "C29", capacitance: "0.1uF", footprint: "cap0201", rail: "VDD2", region: "VDD2", target: { component: "U2", ball: "R1", signal: "VDD2_R1", physicalPin: 121 } },
{ name: "C30", capacitance: "0.1uF", footprint: "cap0201", rail: "VDDQ", region: "VDDQ", target: { component: "U2", ball: "W1", signal: "VDDQ_W1", physicalPin: 161 } },
{ name: "C31", capacitance: "0.1uF", footprint: "cap0201", rail: "VDD2", region: "VDD2", target: { component: "U2", ball: "R12", signal: "VDD2_R12", physicalPin: 130 } },
{ name: "C32", capacitance: "0.1uF", footprint: "cap0201", rail: "VDDQ", region: "VDDQ", target: { component: "U2", ball: "W12", signal: "VDDQ_W12", physicalPin: 170 } },
{ name: "C33", capacitance: "0.1uF", footprint: "cap0201", rail: "VDD1", region: "VDD1", target: { component: "U2", ball: "U1", signal: "VDD1_U1", physicalPin: 141 } },
{ name: "C34", capacitance: "0.1uF", footprint: "cap0201", rail: "VDD2", region: "VDD2", target: { component: "U2", ball: "AB4", signal: "VDD2_AB4", physicalPin: 194 } },
{ name: "C35", capacitance: "0.1uF", footprint: "cap0201", rail: "VDDQ", region: "VDDQ", target: { component: "U2", ball: "AA3", signal: "VDDQ_AA3", physicalPin: 183 } },
{ name: "C36", capacitance: "0.1uF", footprint: "cap0201", rail: "VDD1", region: "VDD1", target: { component: "U2", ball: "U12", signal: "VDD1_U12", physicalPin: 150 } },
{ name: "C37", capacitance: "0.1uF", footprint: "cap0201", rail: "VDD2", region: "VDD2", target: { component: "U2", ball: "AB9", signal: "VDD2_AB9", physicalPin: 197 } },
{ name: "C38", capacitance: "0.1uF", footprint: "cap0201", rail: "VDDQ", region: "VDDQ", target: { component: "U2", ball: "AA10", signal: "VDDQ_AA10", physicalPin: 188 } },
]
const dramBulkDecoupling: readonly FixedBulkCapacitor[] = [
{ name: "C39", capacitance: "10uF", footprint: "cap0603", pcbX: 27, pcbY: -2, pcbRotation: 0, rail: "VDD2" },
{ name: "C40", capacitance: "10uF", footprint: "cap0603", pcbX: 27, pcbY: 2, pcbRotation: 0, rail: "VDDQ" },
]
const socPowerTarget = (signal: string): PowerBallTarget => {
const ball = SOC_POWER_BALLS.find((candidate) => candidate.signal === signal)
if (!ball) throw new Error(`Missing AM62L power/local-CAP ball ${signal}`)
return {
component: "U1",
ball: ball.ball,
signal: ball.signal,
physicalPin: ball.pin,
}
}
const socLocalCapAssignments: readonly AutoPlacedDecouplingCapacitor[] = [
{ name: "C45", capacitance: "0.1uF", footprint: "cap0201", rail: "CAP_VDDS_GENERAL1", region: "LOCAL_CAP", target: socPowerTarget("CAP_VDDS_GENERAL1") },
{ name: "C46", capacitance: "0.1uF", footprint: "cap0201", rail: "CAP_VDDS_MMC0", region: "LOCAL_CAP", target: socPowerTarget("CAP_VDDS_MMC0") },
{ name: "C47", capacitance: "0.1uF", footprint: "cap0201", rail: "CAP_VDDS_GPMC", region: "LOCAL_CAP", target: socPowerTarget("CAP_VDDS_GPMC") },
{ name: "C48", capacitance: "0.1uF", footprint: "cap0201", rail: "CAP_VDDS_MMC2", region: "LOCAL_CAP", target: socPowerTarget("CAP_VDDS_MMC2") },
{ name: "C49", capacitance: "0.1uF", footprint: "cap0201", rail: "CAP_VDDSHV_MMC", region: "LOCAL_CAP", target: socPowerTarget("CAP_VDDSHV_MMC") },
{ name: "C50", capacitance: "0.1uF", footprint: "cap0201", rail: "CAP_VDDS_MMC1", region: "LOCAL_CAP", target: socPowerTarget("CAP_VDDS_MMC1") },
]
const allAutoPlacedDecoupling = [
...socAutoPlacedDecoupling,
...socLocalCapAssignments,
...dramAutoPlacedDecoupling,
] as const
if (allAutoPlacedDecoupling.length !== 40) {
throw new Error("pcbPack experiment must contain exactly 40 auto-placed capacitors")
}
const socLocalCapSignals = new Set(
socLocalCapAssignments.map(({ target }) => target.signal),
)
const socGlobalPowerBalls = SOC_POWER_BALLS.filter(
({ signal }) => !socLocalCapSignals.has(signal),
)
const railForSocPowerSignal = (signal: string) => {
if (signal.startsWith("VDD_CORE")) return "VDD_CORE"
if (signal.startsWith("VDDS_DDR")) return "VDDS_DDR"
if (signal.startsWith("VDDSHV0")) return "VDDSHV0"
if (signal.startsWith("VDDSHV1")) return "VDDSHV1"
return signal
}
if (socGlobalPowerBalls.length + socLocalCapAssignments.length !== 50) {
throw new Error("AM62L supply/local-CAP accounting must equal 50 balls")
}
const pmicPinLabels = {
pin1: "NC1",
pin2: "EN",
pin3: "PGOOD",
pin4: "VDD_RTC",
pin5: "VDD_CORE",
pin6: "VDDS_DDR",
pin7: "VDDS_IO_1V8",
pin8: "VDDS_IO_3V3",
pin9: "VDDS_WKUP",
pin10: "GND1",
pin11: "GND2",
pin12: "FB_CORE",
pin13: "FB_DDR",
pin14: "SDA",
pin15: "SCL",
pin16: "VIN",
pin17: "SYNC",
pin18: "SW1",
pin19: "SW2",
pin20: "NC",
} as const
const pmicConnectedPins = new Set([2, 4, 5, 6, 7, 8, 9, 10, 11, 16])
const pmicCriticalCaps = [
{
name: "C21",
capacitance: "10uF",
footprint: "cap0603" as const,
pcbX: -17,
pcbY: -9.25,
rail: "VIN",
targetSignal: "VIN",
targetPin: 16,
targetPortCenter: [-14.15, -9.25] as const,
},
{
name: "C22",
capacitance: "1uF",
footprint: "cap0402" as const,
pcbX: -16.2,
pcbY: -7.2,
rail: "VIN",
targetSignal: "VIN",
targetPin: 16,
targetPortCenter: [-14.15, -9.25] as const,
},
{
name: "C51",
capacitance: "1uF",
footprint: "cap0402" as const,
pcbX: -7.5,
pcbY: -9.25,
rail: "VDD_CORE",
targetSignal: "VDD_CORE",
targetPin: 5,
targetPortCenter: [-9.85, -9.25] as const,
},
] as const
const ddrBiasPassives = [
{
name: "R1",
role: "SOC_DDR_CAL_TO_GND",
resistance: "240ohm",
target: { component: "U1", ball: "M3", signal: "DDR0_CAL0", physicalPin: 182, ballCenter: [4.5, 0] as const },
pcbX: 3.8,
pcbY: -9,
pcbRotation: 0,
biasNet: "GND",
},
{
name: "R2",
role: "DRAM_ZQ_TO_GND",
resistance: "240ohm",
target: { component: "U2", ball: "A5", signal: "ZQ", physicalPin: 5, ballCenter: [11.175, -1.2] as const },
pcbX: 10.5,
pcbY: -6.8,
pcbRotation: 90,
biasNet: "GND",
},
{
name: "R3",
role: "DRAM_ODT_CA_PULLUP",
resistance: "2.2kohm",
target: { component: "U2", ball: "G2", signal: "ODT_CA", physicalPin: 62, ballCenter: [15.075, -3.6] as const },
pcbX: 15.075,
pcbY: -7.5,
pcbRotation: 90,
biasNet: "VDD2",
},
{
name: "R4",
role: "DRAM_RESET_PULLDOWN",
resistance: "10kohm",
target: { component: "U2", ball: "T11", signal: "RESET_n", physicalPin: 139, ballCenter: [20.925, 3.6] as const },
pcbX: 20.925,
pcbY: 7.5,
pcbRotation: 90,
biasNet: "GND",
},
] as const
const resetSeries = {
name: "R5",
role: "DDR_RESET_SERIES",
resistance: "0ohm",
pcbX: 6.2,
pcbY: -9,
pcbRotation: 0,
soc: { component: "U1", ball: "J2", signal: "DDR0_RESET0_n", physicalPin: 140, ballCenter: [5, -1.5] as const },
dram: { component: "U2", ball: "T11", signal: "RESET_n", physicalPin: 139, ballCenter: [20.925, 3.6] as const },
} as const
const oscillatorMetadata = [
{
name: "Y1",
frequency: "25MHz",
loadCapacitance: "12pF",
pcbX: -1.5,
pcbY: 9.5,
pcbRotation: 0,
xiCap: { name: "C41", pcbX: -2.65, pcbY: 8.2, capacitance: "12pF", layer: "bottom" as const },
xoCap: { name: "C42", pcbX: -0.35, pcbY: 8.2, capacitance: "12pF", layer: "bottom" as const },
xi: { component: "U1", ball: "AC18", signal: "WKUP_OSC0_XI", physicalPin: 368, ballCenter: [-3, 5.5] as const },
xo: { component: "U1", ball: "AC17", signal: "WKUP_OSC0_XO", physicalPin: 367, ballCenter: [-2.5, 5.5] as const },
},
{
name: "Y2",
frequency: "32.768kHz",
loadCapacitance: "9pF",
pcbX: -6,
pcbY: 9.5,
pcbRotation: 0,
xiCap: { name: "C43", pcbX: -7.15, pcbY: 8.2, capacitance: "9pF", layer: "bottom" as const },
xoCap: { name: "C44", pcbX: -4.85, pcbY: 8.2, capacitance: "9pF", layer: "bottom" as const },
xi: { component: "U1", ball: "AC21", signal: "LFOSC0_XI", physicalPin: 371, ballCenter: [-4.5, 5.5] as const },
xo: { component: "U1", ball: "AC20", signal: "LFOSC0_XO", physicalPin: 370, ballCenter: [-4, 5.5] as const },
},
] as const
const socNoConnect = SOC_NC_BALLS.map(({ pin }) => `pin${pin}`)
const socDdrDirectBallBySignal = new Map<
string,
(typeof SOC_DDR_DIRECT_BALLS)[number]
>(
SOC_DDR_DIRECT_BALLS.map((ball) => [ball.signal, ball]),
)
const directDramSignals = new Set(
DDR_CONNECTIONS.map(({ memorySignal }) => memorySignal),
)
const dramNoConnect = ballMap
.map(({ signal }, index) => ({ signal, selector: `pin${index + 1}` }))
.filter(({ signal }) => signal === "NC" || signal === "DNU")
.map(({ selector }) => selector)
const dramGroundBalls = ballMap.filter(({ signal }) => signal === "VSS")
const dramPowerBalls = ballMap.filter(({ signal }) =>
["VDD1", "VDD2", "VDDQ"].includes(signal),
)
const dramDirectBalls = ballMap.filter(({ signal }) =>
directDramSignals.has(signal),
)
if (
dramNoConnect.length +
dramGroundBalls.length +
dramPowerBalls.length +
dramDirectBalls.length +
2 !==
ballMap.length
) {
throw new Error("LPDDR4 200-ball accounting is incomplete")
}
const pmicNoConnect = Array.from({ length: 20 }, (_, index) => index + 1)
.filter((pin) => !pmicConnectedPins.has(pin))
.map((pin) => `pin${pin}`)
// A single multi-port logical trace represents the future continuous ground
// planes. This preserves every ground connection while avoiding hundreds of
// redundant point-to-net Trace objects in placement-only evaluation.
const groundPlaneSelectors = [
...SOC_GROUND_BALLS.map(({ pin }) => `U1.pin${pin}`),
...dramGroundBalls.map(({ ball }) => `U2.${ball}`),
...allAutoPlacedDecoupling.map(({ name }) => `${name}.pin2`),
...socBulkDecoupling.map(({ name }) => `${name}.pin2`),
...pmicCriticalCaps.map(({ name }) => `${name}.pin2`),
...dramBulkDecoupling.map(({ name }) => `${name}.pin2`),
...ddrBiasPassives
.filter(({ biasNet }) => biasNet === "GND")
.map(({ name }) => `${name}.pin2`),
...oscillatorMetadata.flatMap(({ name, xiCap, xoCap }) => [
`${xiCap.name}.pin2`,
`${xoCap.name}.pin2`,
`${name}.pin3`,
`${name}.pin4`,
]),
"U3.GND1",
"U3.GND2",
"net.GND",
]
export default () => (
<board
name="AM62L_SOC_DRAM_6L_PLACEMENT"
width="100mm"
height="80mm"
layers={6}
pcbPack
pcbGap="0.2mm"
routingDisabled
>
<AM62L32
name="U1"
footprintVariant="fccsp_373_anb"
pcbX={0}
pcbY={0}
pcbRotation={180}
noConnect={socNoConnect as any}
noSchematicRepresentation
/>
<MT53E1G16D1ZW
name="U2"
pcbX={18}
pcbY={0}
pcbRotation={90}
noConnect={dramNoConnect as any}
noSchematicRepresentation
/>
<chip
name="U3"
manufacturerPartNumber="PLACEMENT_STUB_MULTI_RAIL_PMIC"
footprint="tssop20_p0.5mm"
pinLabels={pmicPinLabels as any}
noConnect={pmicNoConnect as any}
pcbX={-12}
pcbY={-9}
pcbRotation={180}
noSchematicRepresentation
/>
{allAutoPlacedDecoupling.map((cap) => (
<Fragment key={cap.name}>
<capacitor
name={cap.name}
capacitance={cap.capacitance}
footprint={cap.footprint}
layer="bottom"
/>
<trace
name={`${cap.name}_${cap.target.component}_${cap.target.ball}_${cap.target.signal}`}
from={`${cap.target.component}.pin${cap.target.physicalPin}`}
to={`${cap.name}.pin1`}
/>
<trace
name={`${cap.name}_${cap.rail}`}
from={`${cap.name}.pin1`}
to={`net.${cap.rail}`}
/>
</Fragment>
))}
{socBulkDecoupling.map((cap) => (
<Fragment key={cap.name}>
<capacitor
name={cap.name}
capacitance={cap.capacitance}
footprint={cap.footprint}
pcbX={cap.pcbX}
pcbY={cap.pcbY}
pcbRotation={cap.pcbRotation}
/>
<trace name={`${cap.name}_${cap.rail}`} from={`${cap.name}.pin1`} to={`net.${cap.rail}`} />
</Fragment>
))}
{socGlobalPowerBalls.map((ball) => (
<trace
key={`SOC_POWER_${ball.pin}`}
name={`SOC_${ball.ball}_${ball.signal}`}
from={`U1.pin${ball.pin}`}
to={`net.${railForSocPowerSignal(ball.signal)}`}
/>
))}
{pmicCriticalCaps.map((cap) => (
<Fragment key={cap.name}>
<capacitor
name={cap.name}
capacitance={cap.capacitance}
footprint={cap.footprint}
pcbX={cap.pcbX}
pcbY={cap.pcbY}
pcbRotation={0}
/>
<trace name={`${cap.name}_${cap.rail}`} from={`${cap.name}.pin1`} to={`net.${cap.rail}`} />
</Fragment>
))}
<trace name="PMIC_VIN" from="U3.VIN" to="net.VIN" />
<trace name="PMIC_VDD_CORE" from="U3.VDD_CORE" to="net.VDD_CORE" />
<trace from="U3.VDD_RTC" to="net.VDD_RTC" />
<trace from="U3.VDDS_DDR" to="net.VDDS_DDR" />
<trace from="U3.VDDS_IO_1V8" to="net.VDDS_IO_1V8" />
<trace from="U3.VDDS_IO_3V3" to="net.VDDS_IO_3V3" />
<trace from="U3.VDDS_WKUP" to="net.VDDS_WKUP" />
{dramBulkDecoupling.map((cap) => (
<Fragment key={cap.name}>
<capacitor
name={cap.name}
capacitance={cap.capacitance}
footprint={cap.footprint}
pcbX={cap.pcbX}
pcbY={cap.pcbY}
pcbRotation={cap.pcbRotation}
/>
<trace name={`${cap.name}_${cap.rail}`} from={`${cap.name}.pin1`} to={`net.${cap.rail}`} />
</Fragment>
))}
{dramPowerBalls.map((ball) => (
<trace
key={`DRAM_POWER_${ball.ball}`}
name={`DRAM_${ball.ball}_${ball.signal}`}
from={`U2.${ball.ball}`}
to={`net.${ball.signal}`}
/>
))}
{ddrBiasPassives.map((resistor) => (
<Fragment key={resistor.name}>
<resistor
name={resistor.name}
resistance={resistor.resistance}
footprint="0402"
pcbX={resistor.pcbX}
pcbY={resistor.pcbY}
pcbRotation={resistor.pcbRotation}
/>
<trace
name={`${resistor.name}_${resistor.target.signal}`}
from={`${resistor.target.component}.pin${resistor.target.physicalPin}`}
to={`${resistor.name}.pin1`}
/>
{resistor.biasNet !== "GND" && (
<trace
name={`${resistor.name}_${resistor.biasNet}`}
from={`${resistor.name}.pin2`}
to={`net.${resistor.biasNet}`}
/>
)}
</Fragment>
))}
<resistor
name={resetSeries.name}
resistance={resetSeries.resistance}
footprint="0402"
pcbX={resetSeries.pcbX}
pcbY={resetSeries.pcbY}
pcbRotation={resetSeries.pcbRotation}
/>
<trace
name="DDR_RESET_SOC_TO_SERIES"
from={`U1.pin${resetSeries.soc.physicalPin}`}
to={`${resetSeries.name}.pin1`}
/>
<trace
name="DDR_RESET_SERIES_TO_DRAM"
from={`${resetSeries.name}.pin2`}
to={`U2.${resetSeries.dram.signal}`}
/>
{DDR_CONNECTIONS.filter(
({ socSignal }) => socSignal !== resetSeries.soc.signal,
).map((connection) => (
<trace
key={`DDR_${connection.traceName}`}
name={`DDR_${connection.traceName}`}
from={`U1.pin${socDdrDirectBallBySignal.get(connection.socSignal)!.pin}`}
to={`U2.${connection.memorySignal}`}
/>
))}
{FUNCTIONAL_IO_ASSIGNMENTS.map((assignment) => (
<trace
key={`IO_${assignment.sourcePin}`}
name={`IO_${assignment.sourceBall}_${assignment.sourceSignal}`}
from={`U1.pin${assignment.sourcePin}`}
to={`${assignment.targetRef}.${assignment.targetSignal}`}
/>
))}
{oscillatorMetadata.map((oscillator) => (
<Fragment key={oscillator.name}>
<crystal
name={oscillator.name}
frequency={oscillator.frequency}
loadCapacitance={oscillator.loadCapacitance}
footprint="crystal4_px2.5mm_py2mm"
pcbX={oscillator.pcbX}
pcbY={oscillator.pcbY}
pcbRotation={oscillator.pcbRotation}
/>
<capacitor
name={oscillator.xiCap.name}
capacitance={oscillator.xiCap.capacitance}
footprint="cap0201"
pcbX={oscillator.xiCap.pcbX}
pcbY={oscillator.xiCap.pcbY}
layer={oscillator.xiCap.layer}
pcbRotation={90}
/>
<capacitor
name={oscillator.xoCap.name}
capacitance={oscillator.xoCap.capacitance}
footprint="cap0201"
pcbX={oscillator.xoCap.pcbX}
pcbY={oscillator.xoCap.pcbY}
layer={oscillator.xoCap.layer}
pcbRotation={90}
/>
<trace name={`${oscillator.name}_XI_LOAD`} from={`${oscillator.name}.pin1`} to={`${oscillator.xiCap.name}.pin1`} />
<trace name={`${oscillator.name}_XO_LOAD`} from={`${oscillator.name}.pin2`} to={`${oscillator.xoCap.name}.pin1`} />
</Fragment>
))}
<trace name="GROUND_PLANES" path={groundPlaneSelectors} />
<FakeChipEndpoint groupId="MMC0_EMMC" label="MMC0 / eMMC" footprint="bga64_grid8x8_p0.8mm_w8_h8" pcbX={-38} pcbY={27} labelY={34} />
<FakeHeaderEndpoint groupId="MMC12" label="MMC1 / SD + MMC2" pcbX={-17} pcbY={29.5} labelY={35} />
<FakeChipEndpoint groupId="OSPI_GPMC" label="OSPI / GPMC" footprint="lqfp48_w7_h7_p0.5mm" pcbX={5} pcbY={29} labelY={35} />
<FakeChipEndpoint groupId="DSI" label="DSI DISPLAY" footprint="tqfp32_w7_h7_p0.8mm" pcbX={24} pcbY={22} pcbRotation={180} labelY={28} />
<FakeChipEndpoint groupId="USB0" label="USB0 PHY / CONN" footprint="tssop20_p0.5mm" pcbX={-42} pcbY={10} pcbRotation={90} labelX={-39} labelY={17} />
<FakeChipEndpoint groupId="USB1" label="USB1 PHY / CONN" footprint="tssop20_p0.5mm" pcbX={-42} pcbY={-11} pcbRotation={90} labelX={-39} labelY={-4} />
<FakeChipEndpoint groupId="RGMII1" label="RGMII1 PHY" footprint="tqfp32_w7_h7_p0.8mm" pcbX={33} pcbY={11} pcbRotation={90} labelX={36} labelY={17} />
<FakeChipEndpoint groupId="RGMII2_MDIO" label="RGMII2 PHY + MDIO" footprint="tqfp32_w7_h7_p0.8mm" pcbX={33} pcbY={-10} pcbRotation={90} labelX={36} labelY={-4} />
<FakeChipEndpoint groupId="MCASP_SPI" label="MCASP / SPI" footprint="tssop20_p0.5mm" pcbX={-34} pcbY={-28} labelY={-34} />
<FakeChipEndpoint groupId="SERIAL_ADC" label="I2C / UART / MCAN / ADC" footprint="lqfp48_w7_h7_p0.5mm" pcbX={-7} pcbY={-29} labelY={-36} />
<FakeHeaderEndpoint groupId="JTAG_RESET_WAKE" label="JTAG / RESET / WAKE" pcbX={19} pcbY={-29} labelY={-36} />
<silkscreentext text="AM62L32" pcbX={0} pcbY={14.5} fontSize="1mm" anchorAlignment="center" />
<silkscreentext text="LPDDR4 x16" pcbX={18} pcbY={9} fontSize="1mm" anchorAlignment="center" />
<silkscreentext text="PMIC + LOCAL BULK" pcbX={-12} pcbY={-14} fontSize="0.75mm" anchorAlignment="center" />
<silkscreentext text="CORE / DDR / PLL / IO / RTC DECOUPLING" pcbX={-1} pcbY={-13} fontSize="0.65mm" anchorAlignment="center" />
<silkscreentext text="DDR POWER DECOUPLING" pcbX={20} pcbY={-10} fontSize="0.65mm" anchorAlignment="center" />
<silkscreentext text="CAL + RESET LAUNCH" pcbX={5} pcbY={-11.5} fontSize="0.55mm" anchorAlignment="center" />
<silkscreentext text="ZQ" pcbX={10.5} pcbY={-7.8} fontSize="0.5mm" anchorAlignment="center" />
<silkscreentext text="ODT" pcbX={15.1} pcbY={-8.3} fontSize="0.5mm" anchorAlignment="center" />
<silkscreentext text="RESET PD" pcbX={20.9} pcbY={8.3} fontSize="0.5mm" anchorAlignment="center" />
<silkscreentext text="25MHz + LOAD" pcbX={-1.5} pcbY={12} fontSize="0.55mm" anchorAlignment="center" />
<silkscreentext text="32k + LOAD" pcbX={-6} pcbY={12} fontSize="0.55mm" anchorAlignment="center" />
<silkscreentext
text="6L PLACEMENT: L1 SIG / L2 GND / L3 SIG / L4 PWR / L5 GND / L6 SIG"
pcbX={0}
pcbY={38}
fontSize="0.8mm"
anchorAlignment="center"
/>
</board>
)