0hmX/am62l-lpddr4-breakout-repro

RESULTS.md

# Routing results

## Before — registry release 1.0.7

- `tscircuit`: `0.0.2332`
- `@tscircuit/core`: `0.0.1685`
- Byte-1 buses had no `preferredLayer` assignments.
- The focused fanouts completed, but DQ9 and DQ10 exited on `inner2` at the SoC
  and `bottom` at the RAM.
- The published 1.0.7 registry build failed and did not produce a current PCB
  preview.

## After — 2026-08-19

- `tscircuit`: `0.0.2358`
- `@tscircuit/core`: `0.0.1707`
- Core npm `gitHead`: `911a81750403dbc93ddf5d971f952d528a5ec4bd`
- Both breakout paddings: 2 mm
- Autorouter effort: `1x` (the previous `10x` setting exceeded the registry's
  300-second per-file build limit)
- Global autorouter: built-in `beta_pipeline9`
- Global routing is split across the same four byte-1 bus groups to keep each
  capacity-autorouter phase small and deterministic.
- Byte-1 shared bus preferences:
  - DQ9, DQ10: `inner2`
  - DQ11, DQ12, DQ14: `bottom`
  - DQ8, DQ13, DQS1, DQS1_n: `inner3`
  - DQ15, DM1: `inner2`

The same bus declarations are consumed by both breakout autorouting phases, so
each preference applies to the SoC and RAM ends together.

## Verification

- TypeScript: passed
- Netlist: 0 errors, 0 warnings
- Schematic placement: passed
- PCB placement: 0 errors, 0 warnings
- SoC fanout: 11/11 traces, 0 errors
- RAM fanout: 11/11 traces, 0 errors
- Global route: 11/11 traces, 0 autorouter errors
- Fresh cloud-equivalent focused build on `tscircuit@0.0.2358`: passed in
  136.3 seconds
- Layer comparison: 11/11 SoC/RAM pairs matched
- Copper shorts: none detected

The complete route currently reports two via-to-trace clearance diagnostics at
the SoC fanout: 0.004 mm beside DQ9 and 0.021 mm beside DQ15, against the
configured 0.05 mm minimum. Neither is a copper short. This reproduction still
omits the electrical and manufacturing constraints listed in the README and is
not a production DDR layout.