# AM3352 DDR Track B — engineering WIP PCB preview
**Partial full-board preview: 11 of 47 DDR signal nets routed; power and interfaces incomplete. Fabrication and electrical release blocked.**
316 components, 12 trace records, 48 ordinary through-vias, 4 filled pours. Byte0 geometric length spread 0.600 mm; strobe mismatch 0.126 mm. All 62 sampled reference-coverage overlaps are real antipad void overlaps. Local ground/bypass connections, 36 DDR signals, power and interfaces remain incomplete. Full-board Core DRC was disabled for this manual preview; selected and independent checks do not qualify fabrication.
The default public PCB reads the exact saved routed `routed/circuit.json`: SHA-256 `58e8e92084f182d4dc9bbf47cd963e29fdc8fa767a3e7b9505609b3bcbec5beb`. The hosted build reconstructs the saved bytes, exports a viewer from JSON, verifies every record, and preserves the original bytes in `dist/routed/circuit.json`. It does not reroute the authored TSX.
`index.tsx` and its local source dependencies are included unchanged. Original src/index.tsx with savedByte0=true. Owner scripts/build.tsx byte0-board applied PMIC stencil, full-span via export and pour refill; the saved JSON is authoritative.
Frozen checkpoint: `aaeeabb`. The source and copper hashes, counts and status are recorded in `frozen-preview-manifest.json`. The registry upload uses small gzip transport chunks; run `bun scripts/reconstruct.mjs` after cloning to recover the exact routed JSON.
This is a public preview of incomplete engineering work. Full-board electrical, signal-integrity, manufacturing, assembly, footprint and startup/firmware qualification remain open.
The original published b28 baseline remains at https://tscircuit.com/0hmX/am3352-ethernet-rgb-b28-987 and is not overwritten by this package.