0hmX/am3352-ddr-track-b-byte0-wip-20261007

saved-dq.tsx

import { Fragment } from "react"
import { traceProps } from "@tscircuit/props"
import savedPaths from "./contracts/saved-dq-paths.json"

export const savedDqNets = new Set(savedPaths.map(path => path.net))

// Measured eight-DQ solver output, expressed in the CPU footprint frame. CPU/RAM
// relative placement is identical to the diagnostic. The default preserves the
// original unmatched checkpoint; callers may supply separately measured paths.
export function SavedDqRouting({ paths = savedPaths, traceWidth = 0.170688 }: { paths?: typeof savedPaths; traceWidth?: number } = {}) {
  return <>{paths.map(path => <Fragment key={path.net}><trace {...traceProps.parse({
    name: `SAVED_${path.net}`, thickness: traceWidth,
    path: [`.U_CPU > .${path.cpuBall}`, `.U_DDR > .${path.ramBall}`, `net.${path.net}`],
    pcbPathRelativeTo: `.U_CPU > .${path.cpuBall}`, pcbPath: path.points,
  })} /></Fragment>)}</>
}

export function DdrPlaneFeed() {
  return <>
    <via name="DDR1V5_FEED" pcbX={-21.2} pcbY={11.0} fromLayer="top" toLayer="bottom"
      holeDiameter={0.2} outerDiameter={0.4} connectsTo="net.DDR_1V5" />
    <trace name="DDR1V5_CPU_FEED" path={[".U_CPU > .E5", ".DDR1V5_FEED > .top", "net.DDR_1V5"]}
      thickness={0.181356} pcbPathRelativeTo=".U_CPU > .E5" pcbPath={[{ x: -3.2, y: -4 }]} />
  </>
}