0hmX/am3352-ddr-track-b-byte0-wip-20261007
Partial full-board preview: 11 of 47 DDR signal nets routed; power and interfaces incomplete. Fabrication and electrical release blocked.
- Version
- 0.0.1
- License
- unset
- Stars
- 0
ddr-nets.ts
import cpuBallMap from "./contracts/cpu-ballmap.json"
import ramBallMap from "./contracts/ram-ballmap.json"
const signalNets: Record<string, string> = {
ODT: "DDR_ODT", CKE: "DDR_CKE", CK: "DDR_CK", N_CK: "DDR_CKn",
N_CS: "DDR_CSn0", N_RESET: "DDR_RESETn", N_RAS: "DDR_RASn",
N_CAS: "DDR_CASn", N_WE: "DDR_WEn", DML: "DDR_DQM0", DMU: "DDR_DQM1",
DQSL: "DDR_DQS0", N_DQSl: "DDR_DQSn0", DQSU: "DDR_DQS1", N_DQSU: "DDR_DQSn1", ZQ: "DDR_ZQ",
}
export function ramNet(signal: string): string | undefined {
if (signal.startsWith("VSS")) return "GND"
if (signal.startsWith("VDD")) return "DDR_1V5"
if (signal.startsWith("VREF")) return "DDR_VREF"
if (/^DQL\d/.test(signal)) return `DDR_D${signal.slice(3)}`
if (/^DQU\d/.test(signal)) return `DDR_D${8 + Number(signal.slice(3))}`
if (/^A\d+$|^BA\d/.test(signal)) return `DDR_${signal}`
return signalNets[signal]
}
export const ddrConnections = Object.entries(ramBallMap).flatMap(([ramBall, signal]) => {
const net = ramNet(signal)
const cpuBall = Object.entries(cpuBallMap).find(([, cpuSignal]) => cpuSignal === net)?.[0]
return net && cpuBall && !["GND", "DDR_1V5", "DDR_VREF"].includes(net) ? [{ net, cpuBall, ramBall }] : []
})
export const ramConnections = Object.fromEntries(Object.entries(ramBallMap).flatMap(([ball, signal]) => {
const net = ramNet(signal)
return net ? [[ball, `net.${net}`]] : []
}))
export const ramNoConnect = Object.entries(ramBallMap).filter(([, signal]) => !ramNet(signal)).map(([ball]) => ball)