seveibar/am3352-ram-dogbone-and-single-layer-route-test

AM3352BZCZ100 processor connected to a W631GG6MB-12 DDR3 memory chip through a routed, length-matched 16-bit DDR interface with clock/data-strobe pairs and control/address signals.

Version: 0.0.9
License: unset
Stars: 0

scripts/test-pair-coupling.py

import importlib.util,json,copy
from pathlib import Path
p=Path(__file__).with_name('audit-pair-coupling.py');spec=importlib.util.spec_from_file_location('coupling',p);m=importlib.util.module_from_spec(spec);spec.loader.exec_module(m)
c=json.loads((p.parent.parent/'dist/index/circuit.json').read_text());assert m.audit(c)['status']=='PASS'
# Preserve length exactly while moving a main route away from its partner.
bad=copy.deepcopy(c)
for t in bad:
 if t['type']=='pcb_trace' and t['source_trace_id']=='source_trace_15':
  for q in t['route']:
   if q.get('layer')=='inner1':q['x']+=.4
r=m.audit(bad);assert r['status']=='FAIL';assert r['pairs'][0]['planarSkewMm']<.127;assert any(t['interiorViolatingSamples']>0 for t in r['pairs'][0]['members'])
print('PASS: pair separation fails independently of passing length skew')