seveibar/am3352-ram-dogbone-and-single-layer-route-test
AM3352BZCZ100 processor connected to a W631GG6MB-12 DDR3 memory chip through a routed, length-matched 16-bit DDR interface with clock/data-strobe pairs and control/address signals.
- Version
- 0.0.9
- License
- unset
- Stars
- 0
scripts/test-route-turns.py
import importlib.util,math
from pathlib import Path
p=Path(__file__).with_name('audit-route-turns.py');spec=importlib.util.spec_from_file_location('turns',p);m=importlib.util.module_from_spec(spec);spec.loader.exec_module(m)
stairs=[(0,0),(0,1),(.1,1.1),(.1,1.2),(1,2.1),(1,2.2),(1.8,3)]
simple=[(0,0),(0,1.2),(1.8,3)]
assert abs(sum(math.dist(a,b)for a,b in zip(stairs,stairs[1:]))-sum(math.dist(a,b)for a,b in zip(simple,simple[1:])))<1e-10
assert m.score(stairs)['ordinaryTurns']==5 and m.score(simple)['ordinaryTurns']==1
assert m.score(stairs)['shortJogSegments']==3
arc=[(math.cos(math.radians(a)),math.sin(math.radians(a)))for a in range(0,91,5)]
assert m.score(arc)['ordinaryTurns']==0
assert m.score([(0,0),(0,1),(0,2)])['ordinaryTurns']==0
print('PASS: stair-step turns, length-preserving replacement, short jogs, collinear points and curved-meander exclusion')