mohan-bee/flight-controller-v2

A 64 mm STM32F405 flight-controller PCB with ICM-42688 IMU, SPI flash, USB-C/ESD, battery buck and 3.3 V regulation, four motor outputs, service I/O, and PETG standoff mounting hardware.

Version
0.1.0
License
ISC
Stars
0

validation/release/first-route-build.txt


> flight-controller-v2@1.0.0 build
> tsci build index.circuit.tsx --site --pcb-png --pcb-svgs --schematic-svgs --disable-parts-engine

Building 1 file(s)...
Building index.circuit.tsx...
Generating circuit JSON...
Could not save autorouting paths for subcircuit_source_group_0: PCB port selector is not unique: .U7 > port.pin4
Circuit JSON written to dist/index/circuit.json
The "J" prefix is being used with a <chip />, try using it with a <connector /> or <jumper />
The "J" prefix is being used with a <chip />, try using it with a <connector /> or <jumper />
The "J" prefix is being used with a <chip />, try using it with a <connector /> or <jumper />
The "J" prefix is being used with a <chip />, try using it with a <connector /> or <jumper />
The "J" prefix is being used with a <chip />, try using it with a <connector /> or <jumper />
The "J" prefix is being used with a <chip />, try using it with a <connector /> or <jumper />
The "J" prefix is being used with a <chip />, try using it with a <connector /> or <jumper />
Port pin17 on J_USB is missing a trace
Port pin23 on J_USB is missing a trace
Port pin1 on J_USB is missing a trace
Port pin2 on J_USB is missing a trace
Port pin3 on J_USB is missing a trace
Port pin4 on J_USB is missing a trace
Port pin5 on J_USB is missing a trace
Port pin6 on J_USB is missing a trace
Port pin7 on J_USB is missing a trace
Port pin8 on J_USB is missing a trace
Port pin9 on J_USB is missing a trace
Port pin10 on J_USB is missing a trace
Port pin11 on J_USB is missing a trace
Port pin12 on J_USB is missing a trace
U7 has no pin with requires_power=true
J_BAT has no pin with requires_power=true
J_BAT has no pin with requires_ground=true
All pins on J_BAT are underspecified (no pinAttributes set)
J_SWD has no pin with requires_power=true
J_SWD has no pin with requires_ground=true
All pins on J_SWD are underspecified (no pinAttributes set)
J_AUX has no pin with requires_power=true
J_AUX has no pin with requires_ground=true
All pins on J_AUX are underspecified (no pinAttributes set)
J_M1 has no pin with requires_power=true
J_M1 has no pin with requires_ground=true
All pins on J_M1 are underspecified (no pinAttributes set)
J_M2 has no pin with requires_power=true
J_M2 has no pin with requires_ground=true
All pins on J_M2 are underspecified (no pinAttributes set)
J_M3 has no pin with requires_power=true
J_M3 has no pin with requires_ground=true
All pins on J_M3 are underspecified (no pinAttributes set)
J_M4 has no pin with requires_power=true
J_M4 has no pin with requires_ground=true
All pins on J_M4 are underspecified (no pinAttributes set)
J_USB has no courtyard
J_BAT has no courtyard
J_SWD has no courtyard
J_AUX has no courtyard
J_M1 has no courtyard
J_M2 has no courtyard
J_M3 has no courtyard
J_M4 has no courtyard
Trace [.U5 > .pin3 to .U5 > .pin1] is routed thinner than requested (requested: 0.25mm, actual: 0.15mm).
.C_OUT2 > .pin2 to net.GND has a 6.00 mm segment on top at 161.47°, 18.53° from the nearest allowed direction (180°). Prefer a multiple of 45° for segments longer than 5 mm (tolerance 4°).
.J_RX > .pin2 to net.GND has a 8.52 mm segment on top at 114.25°, 20.75° from the nearest allowed direction (135°). Prefer a multiple of 45° for segments longer than 5 mm (tolerance 4°).
PCB trace .C_GYRO_IN > .pin1 to net.V5_SYS is too close to .J_RX > .pin2 to net.GND (gap: 0.193mm)
PCB trace .C_GYRO_IN > .pin1 to net.V5_SYS overlaps with pcb_plated_hole "J_RX.RX_RX" (accidental contact)
PCB trace .C_GYRO_IN > .pin1 to net.V5_SYS is too close to .U1 > .pin30 to net.RX_RX (gap: 0.004mm)
PCB trace .C_GYRO_IN > .pin1 to net.V5_SYS overlaps with pcb_plated_hole "J_RX.GND" (accidental contact)
PCB trace .U1 > .pin29 to net.RX_TX is too close to .U1 > .pin30 to net.RX_RX (gap: 0.195mm)
PCB trace .U1 > .pin30 to net.RX_RX overlaps with pcb_plated_hole "J_RX.RX_TX" (accidental contact)
Pad J_RX.RX_RX and trace .J_RX > .pin2 to net.GND are too close (clearance: 0.068mm, minimum: 0.2mm)
Generating preview images...
[index] Generating PCB SVG...
[index] Written pcb.svg
[index] Generating PCB PNG...
[index] Written pcb.png
[index] Generating schematic SVG...
[index] Written schematic.svg
Generating 3D preview images for all site builds...

Build complete
  Circuits  0 passed 1 failed
  Options   site, pcb-png, pcb-svgs, schematic-svgs
  Output    dist

⚠ Build completed with errors
Build exiting with code 1: circuit build errors occurred