README.md
# Watchy E-Ink Smartwatch
Four-layer tscircuit Watchy v3 prototype with three automatic schematic sheets and locally bundled component models.
## Current status — 2026-10-11
Do not fabricate or publish this prototype as production-ready. The native autorouter completed with 184 traces and 123 vias on four copper layers, nominally 1.0 mm thick, with zero native PCB errors. Independent checks pass all seven clock/RF top-only/no-via rules. Thirteen non-interface components were previously repositioned or rotated; the battery, USB, display connector, motor, four buttons, MCU and antenna remain fixed. The display-assembly update leaves the PCB outline, pads, holes, traces and vias unchanged. There are 38 warnings: four schematic/part warnings and 34 PCB warnings. Checks and limits are not suppressed or relaxed. Typecheck and fifteen regression tests pass; the complete schematic-warning and mechanical checks do not.
All 53 nets match the official v3 KiCad netlist. The reference has 235 connected pins; two existing additional test points, TP8/TP9, give 237 in this project. All 52 checked R/C/L quantities and crystal frequencies match the official schematic. This does not qualify purchasable MPNs, tolerances, crystal loading, signal integrity or functionality.
The display now uses native `assembly.screen`, attached to J3's native cable-insertion frame, with a Modelprinter `flexscreen` fold through the existing lower strap slot. The rigid `Display.step` is retained only as a historical reference, not rendered. Panel dimensions, flex length and connector contact pitch come from the GDEY0154D67 drawing. This is a parametric assembly proposal, not exact manufacturer CAD: the asymmetric panel bezel, widening flex outline, bend strain, adhesive and contact compliance remain unqualified.
All 76 model envelopes load. The proposed fold clears the PCB and unrelated components. One positive-volume contact remains at the C11092 mating interface; it is retained as a finding, not excluded from the check. The native generated screen mesh is non-manifold at the bezel Boolean faces. The audit additionally evaluates the union of all 912 native JSCAD primitives after standard T-junction triangulation, without removing any solid or patching dependencies. Original renderer errors remain recorded. Earlier C16/battery connector and C27/motor contacts are also clear.
The USB model/PCB contact is now clear after correcting the model origin from both mounting-row datums and the five flat solder-contact undersides. All four tab datums register within 0.05 mm, and every contact underside lands inside its native copper pad. The native 180-degree rotation, footprint and supplied model geometry are unchanged. This is a registration correction, not an artificial clearance lift. See `reports/usb-registration.json`; exact purchased-part geometry and fabrication tolerances are still unqualified.
A direct screen of the supplied KiCad STEP exports found display flex/PCB and display flex/connector intersections. Matching that old rigid model did not certify the fold. The new assembly uses documented native folding parameters, not model cutting, scaling, hiding or an extra PCB cutout. A physical folded-display prototype and supplier-approved bending limits remain necessary; the strap slot must also be tested with the intended watch strap.
The remaining inward-facing warning belongs to J1, the internal battery connector. The installed orientation checker recommends the closest board edge for any horizontal connector; it has no internal-connector exemption. The warning remains visible. No false `from_above` direction or forced outward rotation is used to clear it. See `reports/display-registration.json` for the display correction and warning evidence.
The audit uses Boolean intersections at a 0.001 mm³ threshold, not exact B-rep or manufacturing-envelope certification. Generic display, passive and retained package models do not certify purchased parts. Run `bun run check:mechanical`; failure remains expected for the recorded connector mating contact.
AE1 still lacks the twelve copper polygons forming the official SWRA117D antenna. A two-pad antenna definition is not a working reproduction of the radiator, and native DRC cannot certify its absence. The attempted generic copper-to-pad import produced intentional-contact errors and was not retained. The four-layer configuration still needs manufacturer-approved dielectric dimensions and impedance qualification. RF performance remains unqualified.
No GitHub issue or PR was created for these findings. Current local evidence is in `reports/four-layer-status.json`, `reports/routing-validation.json`, `reports/schematic-validation.json`, `reports/cad-all-model-intersections.json`, and `reports/placement-optimization/tool-findings.json`. Older experiment reports are historical and must not be used to claim the current build passes. These local reports are not required by the circuit's runtime imports.
## Generated schematic and PCB
The three sheets contain thirteen native named sections: ESP32-S3/Clocks/RF; Power/Battery Monitor/USB; and Display/Sensors/Controls. Sheet and section headings are generated by tscircuit. Native MatchPack/matchAdapt automatic layout and the schematic trace solver place components and route schematic wires; no `schX`, `schY`, `schRotation` or manual schematic paths are authored.
U2/U3/U4/U5/U6 use generated chip boxes, and J3 uses native connector labels. The antenna and motor retain imported KiCad artwork. Their imported text is detached from their body in the current generated output, leaving excess space above the Controls circuit. This is reported for an upstream repro, not concealed with manual schematic placement.
PCB component coordinates are explicit, including physical clearance corrections; PCB placement is not claimed to be fully automatic. Every signal route and via is generated by the released native local autorouter. No authored PCB signal paths, manually positioned vias, custom routing phases, external autorouter or dependency/checker patch is used.
Ground regions use the native copper-pour solver on top, inner1, inner2 and bottom with 0.2032 mm clearance, 0.3 mm board-edge/cutout margins, thermal reliefs and solder-mask coverage. The antenna area has a keepout on all four layers. Inner layers also carry autorouted signals; they are not dedicated uninterrupted planes. Crystal/RF logical connections request top-layer routing; current final geometry passes the independent length/via/layer checks. Native route-path export still reports an ambiguous `.J3 > port.GND` selector for the two ground pins; the native circuit JSON builds successfully without importing those saved paths.
## Models and component values
Twelve distinct EasyEDA/JLC models are active across fifteen component references, including exact C11092 display connector and C91146 USB imports. Fresh `tsci import --jlcpcb --download --use-exact-footprint` checks confirm the local display/USB pad and mounting-hole geometries, and both STEP files match the fresh downloads byte-for-byte. See `reports/native-footprint-import-audit.json`. `assets/model-sources.json` lists provenance and exceptions. Remaining passives are native generated packages; retained battery, crystal, motor, inductor and diode models are not claimed as exact EasyEDA component models.
`scripts/fpc-assembly.test.ts` checks all 24 FPC solder-contact underside rectangles and both mounting tabs against the compiled native pads. They register on the nominal PCB surface without moving the connector. `scripts/display-assembly.test.ts` checks native attachment, dimensions and pitch; `scripts/display-clearance.test.ts` checks the fresh mechanical report and preserves the mating-contact finding. Neither certifies the purchased display's fold or contact mechanics.
R12 belongs to the native Clocks section, not RF; its schematic placement remains automatic.
The official v3 schematic specifies C7/C9 = 3 pF, L1 = 7.5 nH, R12 = 1 MΩ, C16/C19 = 26 pF and C17/C18 = 10 pF. Y2 uses a four-pin crystal symbol so grounded case pads are not mistaken for oscillator signals.
Ten e-paper capacitors use separate capacitance and 50 V rating properties. Combining these in a quantity string previously produced incorrect numeric values despite correct-looking labels; the compiled-value audit now passes. L2 is SRN4018-470M, 47 µH, with 600 mA RMS/620 mA saturation metadata from the Bourns datasheet. Remaining BOM and assembly qualification is still required.
## Structure
- `index.circuit.tsx`: board outline, stackup, autorouter and section composition.
- `schematic/*Section.tsx`: functional component and logical connection modules.
- `schematic/SchematicSheets.tsx` and `schematic/config.ts`: sheets and native section identifiers.
- `routing/CrystalRfRouting.tsx`: crystal/RF logical connections and native bus constraints.
- `pcb/BoardCopper.tsx` and `pcb/board-stackup.ts`: native copper/keepout and four-layer stackup.
- `imports/`, `footprints/`, `assets/`, `symbols/`: component definitions and native import assets.
- `mechanical/display-assembly.ts`: native display model parameters and proposed fold.
- `scripts/`, `tests/fixtures/`, `reports/`: validation and rendering evidence.
The PCB configuration module was renamed from `pcb/config.ts` to `pcb/board-stackup.ts` after a browser-only import-resolution failure with the separate `schematic/config.ts`. Native typecheck/build passed before the rename. The browser evaluator/dev-server cause still needs a reduced repro.
## Commands
```sh
bun install
bun run typecheck
bun test scripts
bun run route
bun run check:built
bun scripts/check-schematic.ts dist/index/circuit.json
bun run check:mechanical
bun scripts/render-pcb.ts dist/index/circuit.json outputs/four-layer-routed
bun scripts/render-schematic.ts dist/index/circuit.json outputs/four-layer-schematic
bunx tsci snapshot dist/index/circuit.json --3d --update --disable-parts-engine --camera-preset top-left-corner
bun run dev --port 3020
```
Routing validation passes locally. Schematic-warning and mechanical validation currently exit nonzero for the findings above. Source tests and typecheck passing do not imply a production-ready board. Native previews retain DRC and ratsnest overlays. A registry rebuild may use different released tooling and must be checked separately from this retained local result.
`route:local` uses the installed core unless an explicit `WATCHY_CORE_MODULE` points elsewhere; the current retained build uses released dependencies without patches. Versions: tscircuit 0.0.2727, core 0.0.2048, checks 0.0.233.
## License
MIT
