README.md
# Watchy E-Ink Smartwatch
Two-layer tscircuit Watchy v3 draft with four automatic schematic sheets and locally bundled component models.
## Current status — 2026-10-02
Do not fabricate or publish this draft. The current native autorouter completed with 184 traces and 166 vias on two copper layers, nominally 1.0 mm thick. Physical placement conflicts around the corrected J3 connector courtyard have been cleared, but four final native DRC errors remain: one 11.54 mm crystal route exceeding 10 mm, two crystal routes using vias despite a zero-via limit, and one via with 0.158 mm copper-to-edge clearance where 0.2 mm is required. Independent inspection also detects top-only/no-via violations on RF_ANT, XTAL_40M_FB and XTAL_40M_OUT. There are 38 warnings: four schematic/part warnings and 34 PCB warnings. Checks are not suppressed.
All 53 nets match the official v3 KiCad netlist. The reference has 235 connected pins; two existing additional test points, TP8/TP9, give 237 in this project. All 52 checked R/C/L quantities and crystal frequencies match the official schematic. This does not qualify purchasable MPNs, tolerances, crystal loading, signal integrity or functionality.
The current mechanical screen loads 76 tessellated solids with no missing models. Two significant intersections remain: display flex/PCB and display flex/C11092 connector. All sixteen previous display contacts with unrelated components are cleared. Their cause was this board's backwards display transform and a 1.25 mm planar offset error, not a tscircuit bug. The corrected rear-side planar registration matches the official KiCad export; the nominal native PCB surface is retained. Flex/connector insertion and the remaining PCB contact are not certified or excluded from validation. Earlier C16/battery connector and C27/motor contacts are also clear.
The USB model/PCB contact is now clear after correcting the model origin from both mounting-row datums and the five flat solder-contact undersides. All four tab datums register within 0.05 mm, and every contact underside lands inside its native copper pad. The native 180-degree rotation, footprint and supplied model geometry are unchanged. This is a registration correction, not an artificial clearance lift. See `reports/usb-registration.json`; exact purchased-part geometry and fabrication tolerances are still unqualified.
A direct screen of the supplied KiCad STEP exports also finds display flex/PCB and display flex/connector intersections. Matching that reference therefore does not certify the fold. A verified folded assembly or mechanical fold dimensions are still required. No arbitrary display shift, extra PCB cutout, model scaling/cutting/hiding or checker exclusion is used to claim clearance.
The remaining inward-facing warning belongs to J1, the internal battery connector. The installed orientation checker recommends the closest board edge for any horizontal connector; it has no internal-connector exemption. The warning remains visible. No false `from_above` direction or forced outward rotation is used to clear it. See `reports/display-registration.json` for the display correction and warning evidence.
The screen uses mesh Boolean intersections at a 0.001 mm³ threshold, not exact B-rep or manufacturing-envelope certification. Generic passive and retained package models do not certify purchased parts. Run `bun run check:mechanical`; failure is expected while these findings remain.
AE1 still lacks the twelve copper polygons forming the official SWRA117D antenna. A two-pad antenna definition is not a working reproduction of the radiator, and native DRC cannot certify its absence. The attempted generic copper-to-pad import produced intentional-contact errors and was not retained. The requested two-layer stackup also differs from the official v3 four-layer stackup. RF performance remains unqualified.
No GitHub issue, PR or upload was created. Current evidence is in `reports/production-status.json`, `reports/routing-validation.json`, `reports/schematic-validation.json`, `reports/cad-all-model-intersections.json`, and `reports/tscircuit-pr-candidates.json`. Older experiment reports are historical and must not be used to claim the current build passes.
## Generated schematic and PCB
The four sheets contain thirteen native named sections: ESP32-S3/Clocks/RF, E-Paper Display/Driver, Power/Battery Monitor/USB, and Sensors/Buttons/Motor. Sheet and section headings are generated by tscircuit. Native matchpack/matchAdapt automatic layout and the schematic trace solver place components and route schematic wires; no `schX`, `schY`, `schRotation` or manual schematic paths are authored.
U2/U3/U4/U5/U6 use generated chip boxes, and J3 uses native connector labels. The antenna and motor retain imported KiCad artwork. Their imported text is detached from their body in the current generated output, leaving excess space above the Controls circuit. This is reported for an upstream repro, not concealed with manual schematic placement.
PCB component coordinates are explicit, including physical clearance corrections; PCB placement is not claimed to be fully automatic. Every signal route and via is generated by the released native local autorouter. No authored PCB signal paths, manually positioned vias, custom routing phases, external autorouter or dependency/checker patch is used.
Ground regions use the native copper-pour solver on top and bottom with 0.2032 mm clearance, 0.3 mm board-edge/cutout margins, thermal reliefs and solder-mask coverage. The antenna area has a top/bottom keepout. Crystal/RF logical connections request top-layer routing; the remaining violations are reported, not bypassed.
## Models and component values
Twelve distinct EasyEDA/JLC models are active across fifteen component references, including exact C11092 display connector and C91146 USB imports. `assets/model-sources.json` lists provenance and exceptions. Remaining passives are native generated packages; retained battery, crystal, motor, inductor and diode models are not claimed as exact EasyEDA component models.
The official v3 schematic specifies C7/C9 = 3 pF, L1 = 7.5 nH, R12 = 1 MΩ, C16/C19 = 26 pF and C17/C18 = 10 pF. Y2 uses a four-pin crystal symbol so grounded case pads are not mistaken for oscillator signals.
Ten e-paper capacitors use separate capacitance and 50 V rating properties. Combining these in a quantity string previously produced incorrect numeric values despite correct-looking labels; the compiled-value audit now passes. L2 is SRN4018-470M, 47 µH, with 600 mA RMS/620 mA saturation metadata from the Bourns datasheet. Remaining BOM and assembly qualification is still required.
## Structure
- `index.circuit.tsx`: board outline, stackup, autorouter and section composition.
- `schematic/*Section.tsx`: functional component and logical connection modules.
- `schematic/SchematicSheets.tsx` and `schematic/config.ts`: sheets and native section identifiers.
- `routing/CrystalRfRouting.tsx`: crystal/RF logical connections and native bus constraints.
- `pcb/BoardCopper.tsx` and `pcb/board-stackup.ts`: native copper/keepout and two-layer stackup.
- `imports/`, `footprints/`, `assets/`, `symbols/`: component definitions and native import assets.
- `scripts/`, `tests/fixtures/`, `reports/`: validation and rendering evidence.
The PCB configuration module was renamed from `pcb/config.ts` to `pcb/board-stackup.ts` after a browser-only import-resolution failure with the separate `schematic/config.ts`. Native typecheck/build passed before the rename. The browser evaluator/dev-server cause still needs a reduced repro.
## Commands
```sh
bun install
bun run typecheck
bun test scripts/usb-assembly.test.ts scripts/display-assembly.test.ts scripts/automatic-schematic.test.ts scripts/component-ratings.test.ts scripts/native-copper.test.ts
bun run route
bun run check:built
bun scripts/check-schematic.ts dist/index/circuit.json
bun run check:mechanical
bun scripts/render-pcb.ts dist/index/circuit.json outputs/two-layer-routed
bun scripts/render-schematic.ts dist/index/circuit.json outputs/two-layer-schematic
bunx tsci snapshot dist/index/circuit.json --3d --update --disable-parts-engine --camera-preset top-left-corner
bun run dev --port 3020
```
Routing and mechanical validation currently exit nonzero for the findings above. Source tests and typecheck passing do not imply a production-ready board. Native previews retain DRC and ratsnest overlays.
`route:local` uses the installed core unless an explicit `WATCHY_CORE_MODULE` points elsewhere; the current retained build uses released dependencies without patches. Versions: tscircuit 0.0.2727, core 0.0.2048, checks 0.0.233.
## License
MIT
