# Corne keyboard: exact supplier footprints and local routing
**Fabrication status: HOLD.** Exact JLCPCB footprint checks and routing checks pass, but connector copper crosses the outline and the panel exporter loses the keyboard profiles. Via-in-pad, assembly clearances, stack-up and critical signal routing remain release items. See JLC-FOOTPRINT-UPDATE.md and the earlier FABRICATION-REVIEW.md.
Both halves and the `index.circuit.tsx` panel compile with zero raw routing diagnostics. All 152 nets are physically connected, including 91 left and 92 right GND pads. No diagnostic records are filtered. Placement/courtyard exceptions in the imported design mean this is not fabrication sign-off.
## Run
Requirements: Bun 1.3.14, Node.js, Python 3.11 or newer.
```sh
bun install --frozen-lockfile
python3 -m venv .venv
.venv/bin/pip install -r requirements.txt
bun run typecheck
bun run test:routing
bun run test:assembly
bun run build
bun run build:panel
bun run check:footprints
bun run dev
```
`dist/<side>/circuit.json` is raw core output. Validated JSON contains the same records after strict checking. Validation fails on routing/compiler errors, disconnected nets or pour clearance below 0.2 mm.
Routes were generated with capacity-autorouter 0.0.887 and repaired locally. `lib/routing/*-routes.json` stores the reviewed copper. The custom callback rejects changed port placement; changes require rerouting and validation. The current panel has 422 traces and 667 via records, all with 0.45 mm copper pads and 0.20 mm drills. Larger-via repairs adjust escape routes and add six short GND bridges on the right half; both halves pass routing DRC and physical connectivity checks.
## Supplier parts and assembly
All 24 part types have exact JLCPCB/EasyEDA imports. Unmodified import snapshots and hashes are in `vendor/jlc-exact-imports` and `lib/parts/jlc-import-manifest.json`. The verifier compares actual compiled copper/drills against reference parts, including pin identity and side transforms.
There are 46 populated C5333465 hot-swap sockets, including four expansion sockets. All 42 removable `_KEY` switches remain DNP. J3/rJ3 and J4/rJ4 have specific JLCPCB header imports and remain DNP. Logos, solder jumpers and alternative encoder pads are unpopulated PCB features. The assembled BOM contains 82 parts per half, all with supplier codes.
The pinned stock CLI/UI ignores DNP in BOM/PnP downloads. Use `bun run export:gerbers`, which builds and exports individual halves, filters assembly lists, and verifies all fabrication-layer bytes remain unchanged. The script rejects panel input because the exporter omits its individual board profiles. Resolve the fabrication blockers before ordering from any export.
## Local dependency fixes
- `vendor/checks` recognizes copper-pour connectivity, holes, islands, layer separation and drills. See its README and upstream.patch.
- `scripts/patch-core-panel-pour.mjs` corrects core 0.0.1861 selecting the wrong board outline in a panel.
- `scripts/patch-copper-pour-obstacles.mjs` restores polygon pad and pill-hole rectangular-pad clearance in copper-pour-solver 0.0.52.
- `scripts/patch-autorouter.mjs` normalizes a measured sub-micron via transition in capacity-autorouter 0.0.887; larger deviations remain errors.
`bun run dev` rebuilds the browser evaluation worker using those patched dependencies and the supported `RUNFRAME_STANDALONE_FILE_PATH` override. Browser/runtime input hashes are recorded in `.tscircuit/local-runtime/manifest.json`. Pour clearance is 0.21 mm to preserve at least 0.2 mm after curve approximation.
## 3D models
47 OBJ/STEP assets are bundled locally. The 164 assembled components have model records. DNP switches and headers are omitted from the assembled 3D view; all intended footprints and mechanical holes remain. The original model manifest covers the first 43 assets; the four added header assets are listed in jlc-header-model-assets.json.
