README.md
# BOOSTXL-DRV8305EVM (tscircuit)
This project is a tscircuit reference implementation inspired by Texas Instruments' [BOOSTXL-DRV8305EVM](https://www.ti.com/tool/BOOSTXL-DRV8305EVM). It recreates the board's main electrical architecture and LaunchPad XL interface from TI's [BOOSTXL-DRV8305EVM User's Guide](https://www.ti.com/lit/pdf/SLVUAI8).
Public package: [imrishabh18/boostxl-drv8305evm](https://tscircuit.com/imrishabh18/boostxl-drv8305evm). The registry release references UUID-pinned JLCSearch models on tscircuit's model CDN for its interactive 3D view.
## What is included
- 90 mm ร 75 mm, four-layer BoosterPack-style PCB
- DRV8305N three-phase gate driver
- Six CSD18540Q5B N-channel MOSFETs arranged as three half-bridges
- Three 7 mฮฉ low-side current shunts with filtered current-sense outputs
- Phase A/B/C and PVDD resistor-divider voltage sensing
- LMR16006-based 3.3 V buck supply
- 4.4โ45 V input and three-phase motor terminal blocks
- Dual 2ร10 LaunchPad XL headers
- Fault and power LEDs, bulk input capacitance, charge-pump capacitors, ground pours, two lower mounting holes, and silkscreen labels
- Package-specific component courtyards with placement DRC enabled and a courtyard-clean PCB layout
- 0.45 mm minimum via-pad diameter and 0.30 mm minimum via-hole diameter
- Phased autorouting for power, SPI, control, voltage-sense, current-sense, and logic nets
- Explicit short GND escapes into an `inner1` ground plane, plus top and bottom ground pours
- Bulk capacitors at the outer side edges and J3/J4 terminal openings facing the outer top edge
The visible power and interconnect parts below were resolved with `tsci import --jlcpcb`. Their canonical OBJ and STEP URLs include the model revision UUID and are attached directly to the proven logical footprints. This keeps binary model files out of the source package while preserving consistent 3D geometry. A fresh build still needs network access to the tscircuit model CDN and to any externally referenced KiCad footprint definitions that are not already cached.
Each custom part is implemented as a separate component under `imports/`. The root `index.circuit.tsx` is limited to board-level composition, schematic sheets, nets, and routing.
| Reference | Part | JLCPCB/LCSC |
| --- | --- | --- |
| U1 | DRV8305NPHPR | C75602 |
| Q1โQ6 | CSD18540Q5B | C86513 |
| U2 | LMR16006XDDCR | C87080 |
| R4โR6 | HoLLR2512-3W-7mR-1% shunt | C2985710 |
| L1 | SMNR8040-150MT, 15 ยตH | C467156 |
| J1โJ2 | PM254-2-10-Z-8.5 socket | C2897411 |
| J3 | WJ500V-5.08-2P terminal | C8465 |
| J4 | WJ500V-5.08-03P terminal | C72334 |
## LaunchPad XL mapping
The header mapping follows the TI reference schematic.
| J1 pin | Signal | J2 pin | Signal |
| ---: | --- | ---: | --- |
| 2 | 3.3 V | 2 | INH_A |
| 5 | VSEN_A | 3 | SCS |
| 6 | nFAULT | 4 | INL_A |
| 7 | VSEN_B | 6 | INH_B |
| 9 | VSEN_C | 7 | GND |
| 11 | VSEN_PVDD | 8 | INL_B |
| 13 | GND | 9 | PWRGD |
| 14 | SCLK | 10 | INH_C |
| 15 | ISEN_A | 11 | SDI |
| 17 | ISEN_B | 12 | INL_C |
| 19 | ISEN_C | 13 | SDO |
| | | 15 | EN_GATE |
| | | 17 | WAKE |
Unlisted pins are intentionally left unconnected.
## Build and inspect
Requirements: Bun and the dependencies in `package.json`.
```sh
bun install
bun run typecheck
bun run build -- --all-images --ignore-warnings
bun run dev
```
The generated circuit JSON and schematic/PCB/3D previews are written under `dist/index/`. Open the development server to inspect the interactive schematic, PCB, and 3D views.
Routing is enabled. The checked-in build completes every autorouting phase without a `pcb_autorouting_error`, and placement DRC reports no component, courtyard, or outside-board errors. Ground pads use explicit short escapes into an `inner1` plane because a single 43-terminal fanout boundary was unnecessarily congested.
The detailed copper DRC is not clean: it still reports clearance, accidental-contact, and misaligned-via errors, concentrated in the legacy hand-authored DRV8305/half-bridge routes and high-current paths. Treat the routed board as a layout/reference artifact, not a fabrication-ready 15 A design. Those copper routes require focused engineering cleanup and independent review before manufacturing.
## Engineering status and safety
This is a functional reference translation, not a production-ready fabrication release. The design was reconstructed from the published TI schematic and user guide; TI's original CAD archive was not imported. Before fabrication or operation, a qualified power-electronics engineer should review at least:
- MOSFET/shunt thermal performance, copper weight, via arrays, and heatsinking
- high-current copper geometry and connector current ratings
- Kelvin routing for all current-shunt sense pairs
- gate-loop length, switching-node copper, dead time, and EMI behavior
- creepage, clearance, transient protection, reverse-polarity protection, and fusing
- component voltage/current derating and the exact BOM/footprints
- LaunchPad mechanical fit and header orientation
- the remaining copper DRC findings, connectivity, Gerbers, drill files, BOM, and pick-and-place outputs
Do not connect a motor or high-current supply until the board has passed independent design review, current-limited bench bring-up, and appropriate safety testing. The nominal 15 A continuous / 20 A peak figures describe the TI reference platform, not a verified rating for this reconstruction.