This code defines a printed circuit board (PCB) with various surface-mount resistors, capacitors, inductors, and integrated circuits, including power management components and interface connectors, for a TI-based LCD and microSD module using 0603 and other package types.
# BOOSTXL-SHARP128 reconstruction
Status: official TI electrical CAD, board outline, layer count, component placement, and assembly side reconstructed; **routing validation is blocked and this board is not order-ready**.
## Source of truth
- TI product page: https://www.ti.com/tool/BOOSTXL-SHARP128
- TI hardware-design archive: https://www.ti.com/lit/zip/slac778
- Local untouched archive: `reference/ti/SLAC778.zip`
- Local extracted Altium schematic, PCB source, BOM, Gerbers, drill, and release PDFs: `reference/design-files/BOOSTXL-SHARP128_Hardware_Design_Files/`
- Official schematic: `reference/design-files/BOOSTXL-SHARP128_Hardware_Design_Files/Hardware/BOOSTXL-SHARP128(001)_Sch.PDF`
- Official PCB-layer drawing: `reference/design-files/BOOSTXL-SHARP128_Hardware_Design_Files/Hardware/BOOSTXL-SHARP128_PCBlayers.PDF`
- Official Altium sources: `reference/design-files/BOOSTXL-SHARP128_Hardware_Design_Files/Hardware/Cad Source Files/`
## Verified reconstruction
- The source is direct native tscircuit markup in `index.circuit.tsx`; it does not use explicit `<netlabel>` elements or locally invented wrapper components.
- The four meaningful schematic sheets preserve the complete connectivity from TI's one-sheet schematic while keeping imported connector symbols inside the sheet frames.
- TypeScript typecheck, `tsci check source`, and `tsci check netlist` pass with zero source/netlist errors and zero warnings.
- The PCB is 58.42 mm x 35.56 mm, 1.6 mm thick, four-layer, and uses the required `minViaHoleDiameter="0.3mm"` and `minViaPadDiameter="0.45mm"`.
- Component coordinates, rotations, and bottom-side assembly follow the official TI Altium PCB source. The BoosterPack connectors are female receptacles mounted on the bottom side.
- The official LS013B7DH03 LCD outline is represented on the board. The display itself is a separately mounted module whose flex folds to J5; it is not falsely represented as an assembled JLCPCB board part.
- Fitted electrical values are preserved: L1 4.7 uH; C1 22 uF; C2 10 nF; C3 4.7 uF; C4/C5/C6/C8 100 nF; C7 1 uF; R3 133 kOhm; and R7/R8/R11/R12/R14/R16/R18 0 Ohm.
- TI's configuration options remain visibly marked DNP: R1/R2/R4/R5/R6/R9/R13/R15/R17/R19/R20 are 0 Ohm, R10 is 4.7 kOhm, and R21 is 100 kOhm.
## Production parts and footprints
- U1 TPS61222DCKR is JLCPCB/LCSC C116461. Its generated footprinter string was accepted because the copper comparison reached 98.61% IoU.
- J1/J3 and J2/J4 use the exact Samtec SSQ-110-03-T-D catalog model, JLCPCB/LCSC C5379997. The generic match was only 9.93%, so the imported EasyEDA copper was retained.
- J5 uses the exact Hirose FH12-10S-0.5SH(55), JLCPCB/LCSC C506791. The generic match was only 10.47%, so the imported EasyEDA copper was retained.
- J6 uses the exact Hirose DM3BT-DSF-PEJS, JLCPCB/LCSC C597972, with its imported EasyEDA footprint and mechanical model retained.
- L1 uses the exact official Coilcraft EPL3015-472MLB value and Altium pad geometry. No substitute part was invented.
- Native passives carry the official BOM manufacturer part numbers. DNP footprints are present but must remain unpopulated unless a documented configuration requires them.
## Routing and short-check blocker / feature-improvement list
- `tsci check shorts --mode pcb --layer top` completes and reports no top-layer shorts.
- `tsci check shorts --mode pcb --layer bottom` does not complete on this imported-bottom-heavy design within the bounded run. This needs a timeout/progress diagnostic and a recoverable result.
- Gerber-mode `tsci check shorts` aborts with `Inner layer inner1 only supports copper gerbers`, even when `--layer top` or `--layer bottom` is supplied. The checker should honor the selected layer on four-layer boards instead of rejecting unrelated inner layers.
- The exact TI coordinates trigger ten conservative native 0402/0603 courtyard collisions. Placement checking is disabled in the board source to preserve TI's released placements; tscircuit needs configurable courtyard/assembly-clearance policies rather than a single conservative generic rule.
- Importing the official Altium four-layer copper, planes, and vias would be safer than regenerating them. A PcbDoc-to-circuit importer that preserves the released routing and plane stack would materially improve reconstruction fidelity.
Per project policy, work stops on the blocked routing validation and the build queue continues.
## Remaining release blockers
- The generated routing and copper pours are not demonstrated equivalent to TI's released four-layer Gerbers.
- Bottom-layer shorts have not received a completed independent scan.
- The Sharp LCD, foam/adhesive attachment, folded flex, connector locking direction, microSD insertion clearance, and bottom-side BoosterPack stacking height need mechanical review against the official assembly package and real mating hardware.
- Current JLCPCB stock, lifecycle, authorized sourcing, assembly-side support, and DNP configuration must be confirmed at order time.
- Power-up must use current limiting and bench validation of the boost rail, LCD rail selection, SPI signals, EXTCOMIN behavior, microSD detection, and LaunchPad compatibility.
Do not order this reconstruction yet.