README.md
# Open B0067-compatible camera PCB prototype
This tscircuit project was initialized with:
```sh
bunx --bun tscircuit init -y arducam-mini-2mp-plus-b0067-clone
```
It is a documented-part, open-controller hardware prototype for the Arducam
Mini 2MP Plus B0067 interface. It is **not fabrication-ready** and is not a
source-faithful copy of Arducam's proprietary ArduChip implementation.
## Completion status
| Deliverable | Status |
| --- | --- |
| Connector and electrical architecture | Complete; netlist check passes |
| Exact IC/module footprints | Complete; JLC imports or manufacturer drawing |
| PCB placement | Complete; redistributed 32 x 38 mm, 8-layer placement has 0 errors and 0 warnings |
| PCB routing | **Stopped**; default autorouter still exhausted its iterations after redistribution |
| FPGA compatibility logic | **Not implemented** |
| Bench compatibility | **Not tested** |
No alternate/custom autorouter and no manual signal traces are used. The
inner-layer GND and 3.3 V pours in the source do not by themselves make an
unrouted design manufacturable.
## Verified B0067 interface
The current Plus documentation specifies an OV2640 sensor, 1600 x 1200 active
array, 8 MB frame buffer, maximum 8 MHz SPI clock, 3.3 V to 5 V supply/I/O,
and the following header:
| Pin | Signal | Function |
| ---: | --- | --- |
| 1 | CS | SPI slave chip select input |
| 2 | MOSI | SPI input |
| 3 | MISO | SPI output |
| 4 | SCLK | SPI clock input |
| 5 | GND | Ground |
| 6 | VCC | 3.3 V to 5 V input |
| 7 | SDA | OV2640 serial control data |
| 8 | SCL | OV2640 serial control clock |
The two-wire bus connects directly to the sensor. Published addresses `0x60`
write and `0x61` read correspond to 7-bit address `0x30`.
Verified SPI behavior from the application note:
- CS remains asserted for the complete command/data transaction.
- Command bit 7 is read/write and bits 6:0 are the ArduChip register address.
- Register write sends command then data; register read sends command then a
dummy byte.
- Burst FIFO read uses `0x3c`; the first returned byte is dummy data.
- Capture, multiple capture, FIFO burst, rewind, and low-power behavior are
part of the compatibility target.
The official wording is internally inconsistent: it says "SPI mode 0" while
also stating CPOL=0 and CPHA=1, conventionally mode 1. This must be resolved
with a known-good B0067 on a logic analyzer before HDL release.
## Open substitute architecture
The selected controller is `GW2AR-LV18QN88C8/I7` (JLC/LCSC `C380550`), a
popular orderable Gowin FPGA with 64 Mbit (8 MB) embedded SDRAM. An FPGA was
chosen so the SPI slave can eventually reproduce transaction timing exactly;
that is a design decision, not evidence that Arducam uses this device.
The board connects the following logical blocks in the netlist:
- OV2640 8-bit pixel bus, PCLK, HREF, VSYNC, XCLK, reset and power-down to FPGA.
- Host SPI and sensor-control bus through a TXS0108E level translator.
- 3.3 V buck-boost from the 3.3-5 V header input.
- 1.0 V FPGA core buck, filtered PLL rails, 2.8 V sensor analog rail, and
1.3 V sensor core rail.
- 27 MHz oscillator, W25Q64 configuration flash, and JTAG test pads.
Exact FPGA pin assignments are in `index.circuit.tsx`. Functional
compatibility still requires FPGA HDL for the ArduChip register map, capture
sequencer, SDRAM frame buffer, FIFO pointers, burst read path, level-translator
enable, sensor clock/reset sequencing, and all verified SPI operations above.
## Footprint provenance
| Function | Part | JLC/LCSC | Footprint source |
| --- | --- | ---: | --- |
| FPGA + 8 MB SDRAM | GW2AR-LV18QN88C8/I7 | C380550 | Exact JLC import; QN88 pin map checked against Gowin UG115E |
| Level translation | TXS0108EPWR | C17206 | Exact JLC import |
| 3.3 V buck-boost | TPS63031DSKR | C15516 | Exact JLC import |
| 1.0 V buck | TLV62569DBVR | C141836 | Exact JLC import |
| 2.8 V LDO | XC6206P282MR | C347374 | Exact JLC import |
| 1.3 V adjustable LDO | AP2127K-ADJTRG1 | C96343 | Exact JLC import |
| Configuration flash | W25Q64JVSSIQ | C179171 | Exact JLC import |
| 27 MHz oscillator | OT252027MJBA4SL | C669075 | Exact JLC import |
| 1.5 uH inductor | FNR3015S1R5MT | C167745 | Exact JLC import |
| 2.2 uH inductor | WPN4020H2R2MT | C98361 | Exact JLC import |
| 1x8 header | PZ254V-11-08P | C492407 | Exact JLC import |
| 100 nF / 10 nF / 1 uF / 15 pF 0402 | Selected LCSC passives | C1525 / C85735 / C5137473 / C1548 | Exact JLC imports |
| Image sensor | OV02640-VL9A | Not found in JLC catalog | Custom footprint copied from OmniVision CSP2 drawing |
The OV2640 custom footprint uses the published sparse 38-ball map, 0.8 mm
pitch, 5.725 x 6.285 mm body/courtyard, and nominal 0.35 mm balls. The PCB land
diameter is deliberately set to the nominal ball diameter, not guessed from a
photo. Solder-mask and paste apertures still require review by the CSP assembly
vendor.
No lens-holder footprint, mounting studs, or lens geometry were invented. The
published material does not provide an unambiguous land pattern for the exact
holder fitted to the current B0067.
## Mechanical provenance and assumptions
Verified or independently corroborated:
- 34.1 mm length appears in the legacy drawing. A B0067 distributor listing
supplies the otherwise-missing exact 24.4 mm width; current Plus
documentation independently rounds the board to 34 x 24 mm.
- Two 3.0 mm mounting holes, 20.0 mm center spacing, with their centers 2.13 mm
below the top edge.
- Header centerline 2.79 mm above the bottom edge.
- Optical axis is 12.2 mm from the left board edge.
Explicit assumptions/design choices:
- The legacy drawing is not identified as the current B0067 Plus PCB revision.
- The placement engineering variant uses a 32 x 38 mm, eight-copper-layer board,
not the verified 24.4 x 34.1 mm B0067 outline. It is an engineering routing
choice, not a sourced Arducam dimension. The level translator was moved into
the added width. The placement checker reports a minimum component
bound-to-edge distance of 1.33 mm, not a fabrication-clearance claim.
- The top-side projection opposite the bottom-side FPGA is component-free.
FPGA decoupling parts are outside that package projection; their increased
distance is an explicit layout compromise.
- Component designator text and custom board labels are hidden to keep the PCB
silkscreen uncluttered.
- The optical-axis **vertical** coordinate is not dimensioned. This prototype
places it at `(0, 8 mm)` as a layout choice; that coordinate is not claimed
compatible.
- The controller and flash are on the bottom; sensor and power stages use both
sides of an eight-layer board. This is a new architecture, not cloned placement.
- The selected, fully documented PZ254V-11-08P header has 2.54 mm pitch; the
legacy B0067 drawing does not explicitly dimension the original pitch.
- The six 1 mm JTAG/power test pads are designer-defined service features.
## Validation commands
```sh
bun run typecheck
bunx --bun tscircuit check netlist
bunx --bun tscircuit check placement
```
These pass. `bunx --bun tscircuit build --pcb-png` was also attempted on the
redistributed 32 x 38 mm eight-layer variant using only
`autorouter="default"`; it failed in phase 1 with `uB ran out of iterations`.
No alternate solver was attempted, so routing, shorts validation, and
fabrication readiness are intentionally not claimed.
## Primary references
- [Arducam B0067 product page](https://www.arducam.com/product/arducam-2mp-spi-camera-b0067-arduino/)
- [Arducam RP2040/Pico guide](https://docs.arducam.com/Arduino-SPI-camera/Legacy-SPI-camera/Pico/Camera-Module/SPI-Camera/)
- [Legacy ArduCAM Mini 2MP hardware guide](https://cdn.arducam.com/downloads/shields/ArduCAM_Mini_2MP_Camera_Shield_DS.pdf)
- [Arducam hardware application note](https://www.arducam.com/downloads/shields/ArduCAM_Mini_2MP_Camera_Shield_Hardware_Application_Note.pdf)
- [OV2640 datasheet](https://dl.espressif.com/dl/schematics/Camera_OV2640.pdf)
- [Gowin QN88 package/pinout, UG115E](https://cdn.gowinsemi.com.cn/UG115E.pdf)
- [Gowin GW2AR product family](https://gowinsemi.com/en/product/arora-ii-fpga/)
- [Gowin GW2AR documentation database](https://www.gowinsemi.com/en/document/main/database/1846/)
- [Gowin FPGA schematic design guide, UG206](https://www.gowinsemi.com/upload/database_doc/26/document/5b29c9c2c8e22.pdf)
- [TPS63031 datasheet](https://www.ti.com/lit/ds/symlink/tps63031.pdf)
- [TLV62569 product/datasheet page](https://www.ti.com/product/TLV62569)
- [B0067 exact board-size corroboration](https://akizukidenshi.com/catalog/g/g113199/)