README.md
**PCBGolf routing checkpoint — incomplete.** This public development revision adds four required local eFuse output capacitors, closes CAN0_H and four indicator collectors, and improves actual ground spreading. It remains an unfinished, noncompetitive development board; no completed MVP, fabrication, working hardware or validated competition score is claimed.
The native project has 260 references, 255 populated component models, two 2 oz copper layers and a consistent 0.8 mm stackup. All five external USB high-speed links and the hub clock are physically routed. The H725 LQFP100 migration, 4.7 kΩ IMON resistors, 20 pF hub crystal capacitors and local supply bypasses remain. C117–C120 are four actual KEMET C0603C224K5RACTU 220 nF/50 V/X7R OUT capacitors, with reviewed maximum bodies and physical OUT/GND bonds.
Independent native geometry, configured ERC, semantic and raw schematic/PCB parity, numeric process, actual model identity, 77 scoped small signal vias and 145 actual filled/capped VIPs pass. **198 native missing-connection items across 94 physically split nets remain.** The localized native project retains 288 warnings, including dangling fragments, mask/library and silk/text items. ERC retains disclosed inherited ignored checks. An individual saved-polygon graph preserves all 29,060 prior connected pad pairs and verifies all 23 reviewed ground sites reach the actual hub EP. The pre-existing host ground island at J3:A1/J3:B12/J3:MP1 is still separate.
- `index.circuit.json` and `previews/` retain actual native geometry: 1,044 physical pads, 2,617 straight segments, 485 vias and 20 saved fill polygons. Native keepouts and STEP bodies remain authoritative. One inherited unassigned J1 PWR2 source-port metadata entry is disclosed.
- `native/pcbgolf.kicad_pro` opens the self-contained hierarchical schematic and PCB with three local footprint libraries, local symbols, BOM and all 255 model bindings. Actual model bytes, component poses, pad/copper geometry and declared process rules are preserved.
- `downloads/` contains the exact STEP compressed into 10 verified parts to fit registry request limits. Run `python3 downloads/reassemble_step.py` after downloading the package to recover `assembly.step` (SHA256 `b6e152d8f9ff822c0f92a9c2b8d68284b22bb4aed971408495acf86dce1f0cb0`). It includes the exact audited board, copper, mask, 255 actual component bodies and both real mounting-support materials. The selected J1 locator bore measures 1.70 mm. All 32,385 actual component-body pairs clear at least 0.1 mm; all model hashes, unit scales, poses and bounds pass. Envelope: **88.9 × 79.4 × 13.2300001 mm**, volume 93,386.0725 mm³. With 485 vias/two layers, geometry-only arithmetic is 127,636.0725. This is not a validated score.
- `firmware-support/` contains verified pin mapping, ADC calibration/conversion tests and compiled board-support code, not a full linked or flashed application.
- `evidence/` records source-bound native, polygon, process, model, assembly and viewer checks.
Finish all 198 connections, resolve the conservative R43 microSD service conflict, complete firmware/runtime validation and validate the compact replacement assembly. The four required OUT capacitors are now included. The new U13 front ground spreader is 64.91 mm² with 28.35 mm² of rear EP ground; real electrical return routes are independently proved, but these areas do not establish a current/temperature rating. Short USB launch/reference exceptions are disclosed; no controlled-impedance or USB compliance pass is claimed.
Electrical review assumes nominal 12 V and the original 5 A aggregate input boundary. Cooling, automotive surge/load-dump performance and exact filled/capped thin-board fabrication acceptance remain unresolved. Nominal plug envelopes clear other assembly parts; the conservative barrel shoulder allowance overlaps its intended connector, so exact collar registration/tolerances are still unqualified. SD lid/card kinematics remain a TODO. Support load assumptions apply at 23°C; the reviewed 82°C peel case fails. No hot-mating durability or complete hardware qualification is claimed.
Challenge: https://github.com/commaai/PCBGolf . Leaderboard: https://comma.ai/leaderboard . Public package: https://tscircuit.com/0hmX/pcbgolf-routing-checkpoint-20261012 . The native project and hash-qualified STEP are the design authority.
`assembly.tsx` uses tscircuit `assembly.device`, `assembly.subassembly` and actual connector `assembly.part` models to represent this exact frozen assembly in 3D. `assembly.circuit.json` is its compiled CAD view; `index.circuit.json` remains the exact native copper view. All 255 bodies, substrate/copper/mask and both support materials are retained. The view uses one common rigid translation, unit scale and no individual model centering. The large display mesh is partitioned into 31 small files without losing or changing any triangle, material or coordinate. GLB is an inspection tessellation; the hash-qualified STEP remains the exact geometry authority. This is the conservative board; the separate compact modular arrangement is still an incomplete, non-winning engineering study. Routing changes will update both representations after validation.
The default registry preview is the actual assembly CAD view. Open `index.circuit.json` for the native electrical/copper view. The CAD-only view has no electrical routing records, so its viewer error count is not the native connectivity result: **198 native connection items remain**.
Registry package: https://tscircuit.com/0hmX/pcbgolf-routing-checkpoint-20261012 . Revision 0.0.3 retains exactly the native design and viewer of its frozen checkpoint; only the STEP transport is split.
