shibosoftwaredev/f1c100s-linux-nema17-stepper-controller

hardware-validation.md

# First-article electrical validation

This board has passed generated-output checks, but a fabricated assembly must
pass the measurements below before it is treated as a validated motor product.
Record the board serial number, PD supply/cable, firmware revisions, ambient
temperature, motor, load, and oscilloscope screenshots for every test.

## Safe setup

- Use a current-limited, certified USB-PD bench source and begin with the motor
  disconnected and the bridge disabled.
- Use an isolated differential probe for switching-node and phase measurements.
  Never connect a grounded oscilloscope clip to a motor phase.
- Change `R_PD_12V` only with power removed. Keep `R_ISET_210` DNP on this
  software-current revision; fitting it invalidates the nominal mA conversion.
- Confirm there is no short from raw VBUS, switched VBUS, VMOTOR, 5 V, 3.3 V,
  2.8 V, 2.5 V, or 1.2 V to ground before applying power.
- Stop immediately for unexpected heating, smoke, audible arcing, or supply
  current that reaches the bench limit.

## 1. Unpowered and logic-only checks

1. Inspect polarity, soldering, the DRV8825 PowerPAD, all twelve thermal vias,
   USB-C shells, fuse, blocking diode, and TVS orientation.
2. Verify the PD option against the build record and confirm `R_ISET_210` is DNP.
3. Power without a motor. Confirm 5 V, 3.3 V, 2.8 V, 2.5 V, and 1.2 V are in
   tolerance and have no abnormal ripple.
4. Confirm the STM32 holds nSLEEP/nRESET low after reset, loss of UART
   heartbeat, nFAULT, and loss of the valid PD contract.
5. Confirm Linux cannot produce STEP pulses directly and that an unprogrammed
   or stalled STM32 cannot leave the bridge enabled.

## 2. PD selector matrix

Test with power removed between configurations:

| `R_PD_12V` | Required negotiated VM input |
|---|---:|
| DNP | 15 V |
| fitted, 13.3 kΩ | 12 V |

Verify the negotiated voltage before the fuse, after the controlled pass FET,
and at VMOTOR. Confirm a source without the requested PDO does not allow the
motor-enable interlock to arm. Check the pass FET, fuse, diode, TVS, and buck
temperatures during a sustained worst-case logic-and-motor load.

## 3. Software-current matrix and fault checks

Use the matched new PCB and firmware, disarmed with the motor disconnected.
Keep `R_ISET_210` DNP. Set each value with `--set-current-ma`, then query
`--limit` and wait for verified readiness. ACK alone does not mean readiness.
Measure both AVREF/BVREF at the driver and DAC VOUT. Nominal values use the
9.1 kΩ/2.0 kΩ divider and 0.30 Ω regulation shunts:

| Software request | Expected VREF | Nominal peak current/phase |
|---|---:|---:|
| 0 mA | 0 V | 0 A; must not arm |
| 100 mA | 0.150 V | 0.100 A |
| 200 mA | 0.300 V | 0.200 A |
| 300 mA | 0.450 V | 0.300 A |
| 396 mA | 0.594 V | 0.396 A |

Expected DAC VOUT is approximately 8.325 V/A times the requested peak current.
Allow for integer DAC codes and measured VDDA; low supply voltage can saturate
the maximum code, so inspect the reported nominal applied mA too. DRV8825
accuracy below 1 V VREF is degraded: characterize actual coil current rather
than treating these nominal calculations as a calibrated measurement.

Scope nSLEEP/nRESET during cold power-up and MCU resets: the bridge must stay
disabled until zero and the requested setting are written/read-verified and
the reference has settled. Confirm requests while armed return busy, zero
cannot arm, and DAC disconnect/readback errors latch a fault/disable. Verify
settings are volatile and reset restores the requested 396 mA default. Do not
add EEPROM writes to product firmware. A result outside component tolerance
is a stop condition, not an unexplained offset to hide in software.

## 4. Uncoupled-motor tests

1. Fit the specified StepperOnline 17HS13-0404S1 only after verifying each coil
   is approximately 30 Ω and the two coil pairs match the connector table.
2. Begin with a software 200 mA request, verified ready while disarmed, at low
   step rate and with no mechanical load. Verify
   direction, full-step sequence, 1/16 microstepping, controlled stop, immediate
   disable, heartbeat timeout, nFAULT handling, and thermal shutdown.
3. Disarm, select 396 mA and repeat. Test both 12 V and 15 V PD selections.
4. Log the TMP102 reading and independently check the DRV8825, shunts, TVS,
   fuse, blocking diode, pass FET, buck, connector, and motor with a calibrated
   thermocouple or thermal camera. Establish product temperature limits from
   the measured assembly; do not infer them from PCB simulation alone.

## 5. Transient, back-EMF, and shoot-through checks

With differential probes and adequate bandwidth, capture VMOTOR and all motor
phases during start, stop, emergency disable, direction reversal, cable
disconnect, maximum intended speed, and maximum intended mechanical load.

- VMOTOR must remain below the DRV8825 45 V absolute maximum with margin, and
  the 22 V TVS must not enter sustained dissipation.
- Phase overshoot and ringing must not exceed driver or connector ratings.
- Observe supply current and both shunt voltages around every switching edge.
  Reject any cross-conduction signature, unexplained current spike, or mismatch
  between phase current and the selected limit.
- Repeat hot and cold, at minimum and maximum PD input tolerance, and with the
  longest intended motor cable.

Only after these tests pass should the board be exercised with a coupled load.
Repeat the thermal and transient suite at the maximum intended speed, torque,
duty cycle, enclosure temperature, and airflow.

## Added PD-monitor and firmware checks

Perform fault injection with the motor disconnected first. Verify the fitted
TLV75512PDBVR 1.2 V rail under worst-case Linux/DDR workload: it is a 500 mA
regulator, not the previous 600 mA part. Record current, dropout and temperature.

1. Measure raw VBUS and PA1 with a high-impedance meter. The nominal ratio is
   11:1, with about 9.1 ms RC time constant; allow at least 50 ms settling.
   Compare the firmware's mV reading against a calibrated meter at 12 and 15 V.
2. Test a 5 V-only source and unsupported PDO/fallback cases. A measured voltage
   outside 10.8–16.5 V must prevent arming, even if the logic manages to boot.
3. Scope GATE, the BSS138 gate, PB3 and DRV8825 nSLEEP. Verify inverted status,
   valid logic levels, loss-of-contract shutdown, absence of MCU overvoltage,
   and that the added divider does not pull the high-side switch on prematurely.
   Do not drive the VBUS-referenced GATE directly from an MCU or logic generator.
4. Program/read back the boot options as described in `firmware/stm32/README.md`.
   Demonstrate normal flash boot, SWD recovery and a complete F1C100S-initiated
   ROM-UART reflash before relying on the update path.
5. Capture the first STEP edge after arm: it must follow the driver's minimum
   wake time. Measure pulse count/rate, repeat moves in both directions and
   verify duplicate-frame retries cannot execute a move twice.
6. Freeze Linux heartbeats, corrupt frames, disconnect TMP102, assert nFAULT,
   and deliberately stall the MCU main loop in a dedicated test image. Record
   bridge-disable/reset times, fault latching and explicit recovery. Verify
   the independent watchdog over the intended temperature/supply range.
7. Check the actual RGB waveform and colour order, and verify buzzer operation
   without disturbing STEP timing. TMP102 measures local PCB temperature, not
   the DRV8825 junction temperature; correlate it with a thermocouple under load.

## Acceptance record

The release record must include measured rail voltages, both VREF/current
states, both PD states, watchdog/fault timing, maximum temperatures, maximum
VMOTOR/phase excursions, peak input current, and links to scope captures. Any
hardware, motor, cable, firmware timing, stackup, or protection-part change
requires a focused rerun of the affected tests.