shibosoftwaredev/f1c100s-linux-nema17-stepper-controller

SOFTWARE_CURRENT_PROGRESS.md

# Software-adjustable current — local revision, 24 October 2026

Implemented and locally validated, NOT published or fabrication-qualified.
Published latest stays v0.4.55 and its source is untouched. Final evidence:
`reports/software-current-acceptance.json` and `verification.json`.

MCP4725A0T-E/CH (C144198) and a 100 nF / 10 V bypass (C49062) provide a common
nominal 0–396 mA peak/phase setting on the existing MCU I2C bus (0x60; TMP102
stays 0x48). Existing divider/shunts, two-coil telemetry and all GPIOs remain.
The current ceiling is unchanged: this does not support a 1.5 A motor.
`R_ISET_210` stays DNP. New PCB and firmware must be used together.

Linux: `python3 firmware/motor-control.py --set-current-ma 200` sets the limit
without arming/moving; `--limit` reads readiness; `--current-ma 300 --steps 3200
--hz 200` configures before a move. Boot writes/read-verifies zero, then the
requested setting. Arming waits for healthy readback and 3 ms settling; zero
cannot arm. I2C faults/mismatches disable the bridge. No EEPROM writes are used;
reset restores the requested 396 mA default. STEP/IRQ/watchdog and the original
ADC/temperature routines and 0x20/0x21 payloads are byte-preserved.

The four-layer 42.3 mm outline, four mount holes/screw envelopes, both top-side
USB ports, other connectors, top bulk capacitor and complete motor/cable CAD
are unchanged. Three original parts move, retaining their catalog parts:
R_REF_TOP top (-5.25,-13.95), 180 degrees; C_U_2V5_IN bottom (-3.65,-12.51),
90 degrees; C_ETH_1 bottom (1.8,-10.175), 90 degrees, with a shorter rail feed.
New DAC: bottom (-0.75,-14.25), 270 degrees. New bypass: bottom (-3.2,-14.71),
90 degrees. Exact coordinates: `software-current-placement.json`.

Local reference/control/low-current ground routes and the 0.50 mm outer input
elbow are reworked. Actual-metal comparison protects original winding/VM
routes, wide ground outside the three approved former land areas and every
unrelated net/layer. Native source-associated traces retain required verified
session copper; no post-build JSON patch or synthetic island link is used.
Obsolete capacitor fanout/low-current ground cutoffs are removed. Routing
helper/dependencies and fail-closed DRC/input guards are unchanged.

Local gates pass: native errors, all-layer shorts, emitted-only continuity,
independent copper/drills, DFM, Kelvin, solder/paste artwork and both CLI
schematic analyzers. Both PCB faces and the changed motor sheet were inspected.
29 board tests + 32 module tests pass, including an isolated v0.4.55 module
comparison; three sanitizer C suites and 10 Python client tests pass. ARM GCC
14.2 builds the firmware (7336 text / 12 data / 752 BSS bytes). JLCPCB audit
covers 201 populated parts / 85 codes for five boards.

All vias are L1–L4 through-vias, 0.30 mm drill / 0.45 mm pad. The twelfth driver
EP stitch uses the already-specified filled/capped Type VII process. Ordinary
SMT-land/drill intersections are zero. 155 native warnings remain visible:
151 inherited plus four whole-net width diagnostics selecting old 0.12 mm
paths. Dedicated DAC paths are 0.15 mm; the warning report proves this rather
than suppressing native diagnostics or lowering requested widths.

Hardware calibration, thermal/stencil/double-sided reflow approval, USB/Ethernet
signal integrity and actual motor rear-fastening/cable qualification remain
required. No fabrication handoff or publication is approved. PoE is out of scope.

## Historical initial plan — superseded by the validation above

NOT YET BOARD-VALIDATED OR PUBLISHED. Published latest stays v0.4.55.
Baseline source is untouched; its restore-verified checkpoint SHA256 is
`ce32ee8f9dc2463c9b1605727b62970f36880718f0eaeed39ee52ee1f545c024`.

Implemented locally: MCP4725A0T-E/CH (JLCPCB C144198) plus 100 nF 0201 bypass
(Samsung CL03A104KP3NNNC, C49062, 10 V; live orderable stock 653562 when checked);
existing divider/shunts retained, VREF feed moved from DRV3P3 to DAC output.
The DAC shares the motion MCU's I2C bus (0x60, TMP102 stays 0x48).
No new PWM/STEP timing, PoE, board-outline or connector change.

Firmware: disarmed-only 0–396 nominal mA setting (`0x22`), fresh read-only limit
state (`0x23`), verified zero on startup, volatile writes only, 3 ms settle/arm
interlock, periodic DAC register verification and latched fault/disable on error.
Default requested current stays 396 mA. The hardware bridge-disable pulldown,
not EEPROM contents, is the power-on/reset safety mechanism.

Passed so far: sanitizer motion, telemetry and conversion/readback tests;
10 Linux client tests; ARM GCC 14.2 complete firmware build (7336 text / 12 data /
752 BSS bytes); typecheck; original-source contract except the intended reference
feed; native placement 0 errors; website-generation schematic analyzer 0 issues,
and motor sheet visually inspected. Board routing/continuity still IN PROGRESS.
The inherited dist/index/circuit.json is v0.4.55, NOT the new hardware build.
Older copied reports and failed/partial routing candidates are NOT acceptance.

Current placement: DAC bottom (-0.75,-14.25), 270 degrees; new 0201 cap bottom
(-3.2,-14.71), 90 degrees; R_REF_TOP bottom (-1.5,-17.5); existing C_U_2V5_IN
adjusted only (-0.05,+0.06) mm, retaining its value, footprint and face. Outline,
four mount holes, screw envelopes, all connectors, motor/cable assembly and all
other original parts are unchanged. DAC supply is the nearby same regulated
3.3 V rail upstream of fitted R_V3V3_MOTION=0 ohms. Calibration is still required.

Authored real pad escapes pass an independent 0.10 mm copper preflight. These
include the declared same-width outer 0.50 mm BUCK_IN_CAP detour, reworked
low-current ground arcs, a stronger 0.25 mm DRV_GND1 return via C_VMB ground,
and a same-width 0.15 mm inner1 STATUS_DATA_BUFFER_OUT detour. All original
high-current winding/VM trunks are retained. A twelfth full-stack driver EP ground
stitch (-0.85,-12.9) and an ordinary ground stitch (-2.81,-13.145) are explicit.
Existing manufacturing-process.json already specifies filled/capped Type VII
through-vias; tenting alone is not accepted. No blind or buried vias are added.

Outstanding route: new I2C branches compete for a narrow inner2 passage.
The SCL or SDA branch routes by itself, but not both yet. A geometric component
analysis is selecting a legal full-stack transition to put one branch on inner1.
Do NOT retry broad full-board autorouting, modify dependencies or relax DRC.
The bounded tool scripts/route-round7-usb.py has not been changed this turn.
The first complete candidate's physical import found 6 open source connections;
subsequent authored repairs have not yet reached a complete imported candidate.
Every final native source connection must pass with physical_island_links=0.

Tools: Python `/private/tmp/nema17-current-python-WJQ1nu/bin/python` (pinned
requirements plus scipy); ARM prefix
`/private/tmp/nema17-arm-rM2GEX/arm-gnu-toolchain-14.2.rel1-darwin-arm64-arm-none-eabi/bin/arm-none-eabi-`.
The ARM archive matched its official published SHA256 before extraction.
An incomplete temporary extraction was removed and re-extracted after a disk
space failure; no board/checkpoint/user data was deleted.

Before completion: finish actual pad/courtyard/drill-aware placement and routing,
normal full build, netlist/placement/unaffected-copper regression proof, all-layer
shorts, emitted-only continuity, independent copper and drill checks, schematic
visual/style checks, BOM/stock and complete updated firmware tests. Inherited
fabrication qualification gaps remain, regardless of these checks.