muse/book-reading-clip-lamp

routing-notes.txt

Schematic

SAVED ROUTING — LAMP CLIP REV B

The default build imports saved routes through tscircuit's documented custom
algorithmFn interface. This preserves reviewed copper while normal core import,
via expansion, pours, placement/routing checks and exports still run. No design
errors are suppressed. The normal autorouter was observed to place a through-via
under a surface pad when routing between inner layers; therefore every rebuilt
route must undergo the separate shorts check.

saved-routing-input.json is a fresh capture for the direct-FPC Rev B layout.
Previous revision via moves and route replacements are not reused. Any new
corrections are checked against this capture.
saved-routing.ts compares
physical geometry, routing rules and net-to-pad bindings (not only a hash) before replay. Changed board geometry or nets
cause a build failure instead of silently reusing stale copper.
The final capture uses pipeline9 seeds followed by four-layer geometric
rip-up/rerouting and local width expansion. Explicit escapes cover the FPC,
input buffers, control translator and ESP32 pins. Through-vias are treated as copper
on every layer. Two duplicate PCLK paths were removed. The two final source corrections avoid
the rotated USB-C mounting-tab copper and merge a ground via onto the existing
thermal via. The final trace set is checked again by the normal core and
independent Gerber short checks. No DRC rules are disabled.
saved-routing-traces.json is that resulting copper; explicit reviewed via
moves, if needed, live in routing-corrections.json. The helper moves the drill
and both adjacent layer contacts together, then tscircuit validates the result.
Full path replacements live in routing-replacements.json, with one object per
trace: {traceId, originalRoute, replacementRoute, reason}. originalRoute must
match the untouched captured route exactly (object-key order is ignored).
replacementRoute must retain the exact first and last terminal points, use
finite coordinates/positive widths, and change layers only through vias with
coincident wire contacts. The helper changes only route geometry: trace ID,
net connection name and connected-port IDs are preserved. Duplicate targets,
stale originals, altered endpoints and invalid paths fail the build.
The browser and CLI serializers differ in tiny trigonometric rounding,
redundant via aliases and explicitly emitted defaults. Comparison therefore
rounds numbers to 9 decimal places in millimetres, compares named-net bindings
for obstacles, canonicalizes connectivity sets, and materializes the 0.2 mm
trace-to-hole default. Exact pad IDs and coordinates remain checked in the
connection list. saved-routing-holes.json records actual non-plated drill IDs
and geometry so browser-only hole metadata is compared consistently. Changed
geometry, named nets or clearance rules still fail.
verify-routing-guard.ts exercises these cases, including rejected 0.01 mm moves.

Full replacements apply first; via corrections apply afterwards and must match
the resulting path. Every replacement still needs normal clearance/short checks.
The provenance file distinguishes the unrouted input capture from the final
geometry repair and records its routing rules.

After changing component positions, footprints, nets or routing constraints:
1. Run bun run typecheck and all netlist/schematic/placement checks.
2. Run bun run reroute. The CLI-only reroute.circuit.tsx entrypoint uses the normal
   local pipeline9 with fresh-routing.ts and refreshes dist/autorouter-debug.
   Its circuit output is dist/reroute/circuit.json. Browser previews load only
   the guarded saved-route replay, avoiding Node-only solver dependencies.
   Optional trace/via simplification is omitted; detailed paths are retained. Normal topology, detailed routing,
   global repairs, trace widths and all final core/short checks remain enabled.
3. Inspect the build log and copper. Run bun run capture-routing to import that
   geometry as source; this resets both previous via corrections and full route
   replacements, which cannot be safely reused across changed routes. Capturing does not mean the new route is valid.
4. Make any reviewed corrections, rebuild with bun run build, and run
   bun run check:shorts. Also check inner1 and inner2 explicitly.
5. Resolve every routing/short/placement error before sharing revised copper.
   Finish USB impedance, converter-loop, thermal and assembly reviews separately.

The delivered board is an engineering prototype, not an approved Gerber release.
The PCB SVG previews hide inner pours and fade other layers for readability;
dist/index/circuit.json contains the full four-layer geometry.

VIA SIZE UPDATE (0.2.1)
Board minViaHoleDiameter=0.3 mm, minViaPadDiameter=0.45 mm. All explicit
vias and saved-route via points use those exact sizes. The four explicit-via
obstacles and saved routing rules were updated together; all center positions,
trace paths, nets and other clearances are unchanged. Normal input guarding,
core DRC and independent shorts remain enabled.

CLOUD BUILD DISCOVERY (0.2.4)
includeBoardFiles selects only index.circuit.tsx. mainEntrypoint alone does not
restrict automatic board discovery. The previous cloud build also discovered
reroute.circuit.tsx and timed out on that fresh-routing job after1200000 ms;
index.circuit.tsx itself completed successfully. Explicit bun run reroute
remains available, but its convergence and clean DRC are not guaranteed.

INDICATOR FIX (0.2.5)
JLC imports replace the generic status LEDs. Four route endpoints moved less
than0.03 mm, and their port IDs were remapped by original net/polarity. All
other routed paths remain unchanged. Actual updated input was recaptured,
and full parts-enabled build, placement, guard and Gerber shorts repeated.