krishnax12/watchy-eink-smartwatch

reports/tscircuit-pr-candidates.json

{
	"verifiedAt": "2026-10-02",
	"action": "Report only. No GitHub issue, branch, pull request or publication created.",
	"versions": {
		"tscircuit": "0.0.2727",
		"core": "0.0.2048",
		"checks": "0.0.233",
		"browserEval": "0.0.1518"
	},
	"scope": "Five PR candidates observed in the full-board workflow, not five independently isolated root causes. Routing/clearance findings may share a cause. Preserve native checks and do not add manual routes or schematic coordinates as a workaround.",
	"candidates": [
		{
			"id": "routing-constraints",
			"title": "Native autorouting returns traces that violate crystal/via and bus-layer constraints",
			"likelyRepositories": [
				"tscircuit/core",
				"tscircuit/capacity-autorouter"
			],
			"confidence": "Current board-level reproduction; propagation versus solver root cause not isolated.",
			"reproduction": [
				"bun install",
				"bun run route",
				"bun run check:built"
			],
			"expected": "Honor generated crystal max_length=10 and max_via_count=0, and the CRYSTAL_RF bus pcbAllowedLayers=[top].",
			"actual": "XTAL_40M_FB is 11.544172735478213 mm. XTAL_40M_OUT and XTAL_40M_FB each use two vias. Independent inspection also detects a bottom-layer/via route on RF_ANT.",
			"evidence": [
				"routing/CrystalRfRouting.tsx",
				"dist/index/circuit.json",
				"reports/routing-validation.json"
			],
			"isolationNeeded": "Check the current simple-route input, propagation of trace constraints and bus constraints, then reproduce with a reduced crystal/RF circuit. Do not use stale debug input from earlier trials."
		},
		{
			"id": "board-edge-clearance",
			"title": "Autorouter places a via inside the required copper-to-board-edge margin",
			"likelyRepositories": [
				"tscircuit/core",
				"tscircuit/capacity-autorouter"
			],
			"confidence": "Current native final DRC reproduction; router versus cleanup root cause not isolated.",
			"reproduction": [
				"bun run route",
				"bun run check:built"
			],
			"expected": "Via outer copper remains at least 0.2 mm from the board edge.",
			"actual": "pcb_via_19 center x=16.566908505455622 mm, outer diameter=0.35 mm, adjacent board edge x=16.9 mm; gap is approximately 0.15809 mm. Native DRC requires 0.2 mm.",
			"evidence": [
				"dist/index/circuit.json",
				"reports/routing-validation.json",
				"outputs/two-layer-routed-top.png"
			],
			"isolationNeeded": "Reduce the near-edge connection on this board while retaining native via size and board-edge requirements."
		},
		{
			"id": "nonunique-port-selector",
			"title": "Autorouting-path export chooses a non-unique connector pin alias",
			"likelyRepositories": [
				"tscircuit/core"
			],
			"confidence": "Current CLI log and installed implementation agree.",
			"reproduction": [
				"bun run route"
			],
			"expected": "Save route paths using unique numeric pin selectors for distinct pins that legitimately share a GND alias.",
			"actual": "Could not save autorouting paths for subcircuit_source_group_0: PCB port selector is not unique: .J3 > port.GND",
			"detail": "J3 pins 8 and 17 share the real GND signal name. The installed getAutoroutingPhasePcbTracePaths throws when the selected alias does not identify its intended port.",
			"evidence": [
				"imports/FPC24.tsx",
				"node_modules/@tscircuit/core/dist/index.js",
				"dist/index/circuit.json"
			],
			"isolationNeeded": "Build a small connector with two separate GND-labelled pins and export native autorouting paths. This does not invalidate the compiled board's preserved logical netlist, but replay-path export fails."
		},
		{
			"id": "relative-import-resolution",
			"title": "Browser preview fails with separate relative imports sharing the config basename",
			"likelyRepositories": [
				"tscircuit/eval",
				"tscircuit/cli"
			],
			"confidence": "Browser-only full-board observation; isolated import/cache reproduction still needed.",
			"observedError": "schematicSections is not exported by ./config",
			"expected": "schematic/config.ts and pcb/config.ts resolve by their full importer-relative paths.",
			"actual": "Native typecheck/build passed. Browser preview failed until pcb/config.ts was renamed pcb/board-stackup.ts and its imports were updated.",
			"evidence": [
				"schematic/config.ts",
				"pcb/board-stackup.ts",
				"index.circuit.tsx"
			],
			"isolationNeeded": "Use two directories each containing config.ts with different named exports, and compare native versus browser evaluation. Distinguish evaluator caching from dev-server file-key resolution before choosing the PR repository."
		},
		{
			"id": "imported-symbol-artwork-layout",
			"title": "Imported schematic symbol labels remain at local coordinates after automatic placement",
			"likelyRepositories": [
				"tscircuit/core",
				"tscircuit/kicad-to-circuit-json"
			],
			"confidence": "Visible current render and circuit JSON reproduction; import ownership versus layout root cause needs isolation.",
			"reproduction": [
				"bun run route",
				"bun scripts/render-schematic.ts dist/index/circuit.json outputs/two-layer-schematic"
			],
			"expected": "Symbol body, designator and value text move together during native automatic placement.",
			"actual": "M1 body center is approximately (10.84625, -19.15157), but imported M1 label is at (0.2, 0.2) and imported value at (0.2, -0.4). AE1 text is similarly detached. The Controls sheet has excessive empty space above its circuits.",
			"evidence": [
				"symbols/PagerMotor.json",
				"symbols/SWRA117D.json",
				"dist/index/circuit.json",
				"outputs/two-layer-schematic.png"
			],
			"isolationNeeded": "Reduce to one imported motor/antenna symbol with symbol-owned text and matchAdapt layout. Confirm ownership mapping and transform before changing sheet layout."
		}
	],
	"notConfirmedTscircuitBugs": [
		"The previous display-to-ESP32/passive overlaps were caused by this board's backwards CAD rotation and wrong planar offset, now corrected against the official KiCad export. They are not tscircuit bugs. Display/PCB and display/connector model contacts still need verified flex/mating geometry.",
		"EasyEDA C91146 USB mounting/contact registration is corrected using the supplied STEP datums; the native 180-degree rotation is retained. USB/PCB mesh intersection is zero. No converter root cause is claimed; see reports/usb-registration.json for the checked registration and remaining part/tolerance qualification limits.",
		"AE1 currently lacks the twelve copper polygons forming the official SWRA117D antenna. This component definition/import limitation prevents production qualification, but an isolated native copper/net-handling bug has not been established.",
		"Missing courtyards and battery-connector accessibility warnings are part-definition/mechanical qualification problems, not automatically framework bugs.",
		"Previous adjacent-component courtyard and C16/J1 or C27/M1 collisions were board/model placement problems; their retained corrections do not demonstrate framework defects."
	],
	"additionalPolicyLimitations": [
		{
			"title": "Horizontal internal connectors are checked as if they must face the nearest board edge",
			"repository": "tscircuit/checks",
			"confidence": "Installed checkConnectorAccessibleOrientation implementation and a reduced current-J1/board/source-component input confirm this policy. A supported API for internal connector access may require a feature change; not proof the battery connector is mechanically incorrect.",
			"component": "J1",
			"observed": "facing_direction=x-, recommended_facing_direction=x+",
			"expectedUseCase": "An internal battery cable may need to plug in from inside the enclosure rather than through the board edge.",
			"retainedAction": "Warning left visible. No false vertical-insertion metadata, checker patch or forced rotation.",
			"evidence": [
				"reports/display-registration.json",
				"imports/BatteryConnector.tsx",
				"node_modules/@tscircuit/checks/dist/index.js"
			]
		}
	]
}