krishnax12/t113-minimal-linux

ROUTING.md

PCB

Schematic

# PCB routing

Critical SoC, clock, power and USB placements retain their reviewed reference geometry. The UART connector group uses PCB packing. Compatible reference tracks are retained only after checking the current pads and netlist; disconnected branches and redundant prewires are removed.

1. Build `index.circuit.tsx` with `bun run build:source`. Require `scripts/check-schematic.py` and `scripts/check-design.py` to pass.
2. Save that exact build as `routing/source-baseline.json`.
3. Run `bun scripts/add-power-routing.mjs routing/source-baseline.json routing/01-power.json`.
4. Run `bun scripts/add-usb-routing.mjs routing/01-power.json routing/02-usb.json`.
5. Run `python scripts/add-pin-escapes.py routing/02-usb.json routing/03-prewired.json`.
6. Obtain the routed Circuit JSON from Seve's registry release `db504de9-6618-4f5b-8aea-23a6732a330b` (version 0.1.0). Run `python scripts/reuse-reference-routing.py reference-routed.json routing/03-prewired.json routing/04-reference-copper.json`. This rejects conflicting copper and prunes unanchored branches; the report lists connections that still need routing.
7. Run `python scripts/route-remaining.py routing/04-reference-copper.json routed.circuit.json`.
8. Require `python scripts/check-routing.py routed.circuit.json` and `python scripts/check-design.py routed.circuit.json` to pass.
9. Export with `bunx tsci export routed.circuit.json -f gerbers -o dist/fabrication.zip`. Run `python scripts/check-gerbers.py routed.circuit.json dist/fabrication.zip` to compare every exported hole and via to the Circuit JSON.
10. Render and inspect the schematic sheets and PCB layers. Write release evidence with `python scripts/write-validation.py` after all required checks pass.

Use the Python environment installed from `requirements-routing.txt` for these commands. The source baseline and intermediate routing JSON files are local build artifacts and are omitted from the published package.

The remaining-net router searches a 0.1 mm grid on the two outer layers. It treats saved foreign-net copper as immutable obstacles, checks every selected line segment against exact buffered geometry, and permits through vias only where all layers and existing drills have clearance. Signal routes use 0.15 mm width; new power routes use 0.4 mm width. Plane fills are regenerated after routing. The independent physical audit remains the release gate.

The USBLC6 and connector shell contain permanent internal connections. Their pin-number declarations are included in connectivity checks. An exposed-pad or other via-in-pad connection requires filled and capped vias; review those locations with the fabricator. Do not remove electrical or geometric checks to force a pass.