hrithik18k/metal-touch-panel

A PCB autorouting wrapper that corrects footprint-trace obstacle dimensions, solves routes with a preloaded trace-graph solver, and reports completed traces or routing errors.

Version
1.0.0
License
unset
Stars
0

evidence/final-netlist.log

trace: `key` is not a prop. Trying to access it will result in `undefined` being returned. If you need to access the same value within the child component, you should pass it as a different prop. (https://react.dev/link/special-props)
Errors: 0
Warnings: 0

Readable Netlist:
COMPONENTS:
 - U1: LDC1614RGHR
 - C5: 100nF capacitor
 - C6: 1uF capacitor
 - R1: 4.7kΩ resistor
 - R2: 4.7kΩ resistor
 - J1: J1, source_component
 - L1: L1, source_component
 - C1: 1nF capacitor
 - L2: L2, source_component
 - C2: 1nF capacitor
 - L3: L3, source_component
 - C3: 1nF capacitor
 - L4: L4, source_component
 - C4: 1nF capacitor

NET: L1_pos
  - C1 pin1 (+)
  - U1 IN0A
  - L1 pin1 (+)

NET: L1_neg
  - C1 pin2 (-)
  - U1 IN0B
  - L1 pin2 (-)

NET: L2_pos
  - C2 pin1 (+)
  - U1 IN1A
  - L2 pin1 (+)

NET: L2_neg
  - C2 pin2 (-)
  - U1 IN1B
  - L2 pin2 (-)

NET: L3_pos
  - C3 pin1 (+)
  - U1 IN2A
  - L3 pin1 (+)

NET: L3_neg
  - C3 pin2 (-)
  - U1 IN2B
  - L3 pin2 (-)

NET: L4_pos
  - C4 pin1 (+)
  - U1 IN3A
  - L4 pin1 (+)

NET: L4_neg
  - C4 pin2 (-)
  - U1 IN3B
  - L4 pin2 (-)

NET: GND
  - J1 pin2
  - C6 pin2 (-)
  - C5 pin2 (-)
  - U1 SD
  - U1 ADDR
  - U1 CLKIN
  - U1 EP
  - U1 GND

NET: V3V3
  - J1 pin1
  - R2 pin1
  - R1 pin1
  - C6 pin1 (+)
  - C5 pin1 (+)
  - U1 VDD

NET: U1_SCL
  - R1 pin2
  - U1 SCL
  - J1 pin4

NET: U1_SDA
  - R2 pin2
  - U1 SDA
  - J1 pin3

NET: U1_INTB
  - U1 INTB
  - J1 pin5


COMPONENT_PINS:
U1 (LDC1614RGHR)
- pin1(SCL): NETS(U1_SCL)
- pin2(SDA): NETS(U1_SDA)
- pin3(CLKIN): NETS(GND)
- pin4(ADDR): NETS(GND)
- pin5(INTB): NETS(U1_INTB)
- pin6(SD): NETS(GND)
- pin7(VDD): NETS(V3V3)
- pin8(GND): NETS(GND)
- pin9(IN0A): NETS(L1_pos)
- pin10(IN0B): NETS(L1_neg)
- pin11(IN1A): NETS(L2_pos)
- pin12(IN1B): NETS(L2_neg)
- pin13(IN2A): NETS(L3_pos)
- pin14(IN2B): NETS(L3_neg)
- pin15(IN3A): NETS(L4_pos)
- pin16(IN3B): NETS(L4_neg)
- pin17(EP): NETS(GND)

C5 (100nF undefined)
- pin1(anode, pos, left): NETS(V3V3)
- pin2(cathode, neg, right): NETS(GND)

C6 (1uF undefined)
- pin1(anode, pos, left): NETS(V3V3)
- pin2(cathode, neg, right): NETS(GND)

R1 (4.7kΩ undefined)
- pin1(anode, pos, left): NETS(V3V3)
- pin2(cathode, neg, right): NETS(U1_SCL)

R2 (4.7kΩ undefined)
- pin1(anode, pos, left): NETS(V3V3)
- pin2(cathode, neg, right): NETS(U1_SDA)

J1
- pin1: NETS(V3V3)
- pin2: NETS(GND)
- pin3: NETS(U1_SDA)
- pin4: NETS(U1_SCL)
- pin5: NETS(U1_INTB)

L1
- pin1(anode, pos, left): NETS(L1_pos)
- pin2(cathode, neg, right): NETS(L1_neg)

C1 (1nF undefined)
- pin1(anode, pos, left): NETS(L1_pos)
- pin2(cathode, neg, right): NETS(L1_neg)

L2
- pin1(anode, pos, left): NETS(L2_pos)
- pin2(cathode, neg, right): NETS(L2_neg)

C2 (1nF undefined)
- pin1(anode, pos, left): NETS(L2_pos)
- pin2(cathode, neg, right): NETS(L2_neg)

L3
- pin1(anode, pos, left): NETS(L3_pos)
- pin2(cathode, neg, right): NETS(L3_neg)

C3 (1nF undefined)
- pin1(anode, pos, left): NETS(L3_pos)
- pin2(cathode, neg, right): NETS(L3_neg)

L4
- pin1(anode, pos, left): NETS(L4_pos)
- pin2(cathode, neg, right): NETS(L4_neg)

C4 (1nF undefined)
- pin1(anode, pos, left): NETS(L4_pos)
- pin2(cathode, neg, right): NETS(L4_neg)