hrithik18k/metal-touch-panel

evidence/07-routed-build.log

Building 1 file(s)...
Building index.circuit.tsx...
Generating circuit JSON...
trace: `key` is not a prop. Trying to access it will result in `undefined` being returned. If you need to access the same value within the child component, you should pass it as a different prop. (https://react.dev/link/special-props)
Async effect error in PcbTraceRender "autorouting":
Error: getObstaclesFromTrace currently only supports horizontal and vertical traces (not diagonals) Conflicting trace: pcb_trace_0, start: (13.4, -19.2), end: (14.4, -18.6)
    at getObstaclesFromRoute (E:\project\tscircuit\metal-touch-panel\node_modules\@tscircuit\core\dist\index.js:3022:17)
    at getObstaclesFromCircuitJson (E:\project\tscircuit\metal-touch-panel\node_modules\@tscircuit\core\dist\index.js:3489:30)
    at getSimpleRouteJsonFromCircuitJson (E:\project\tscircuit\metal-touch-panel\node_modules\@tscircuit\core\dist\index.js:54706:21)
    at _runLocalAutorouting (E:\project\tscircuit\metal-touch-panel\node_modules\@tscircuit\core\dist\index.js:65675:52)
    at <anonymous> (E:\project\tscircuit\metal-touch-panel\node_modules\@tscircuit\core\dist\index.js:66315:26)
    at _queueAsyncEffect (E:\project\tscircuit\metal-touch-panel\node_modules\@tscircuit\core\dist\index.js:664:16)
    at _startAsyncAutorouting (E:\project\tscircuit\metal-touch-panel\node_modules\@tscircuit\core\dist\index.js:66313:12)
    at doInitialPcbTraceRender (E:\project\tscircuit\metal-touch-panel\node_modules\@tscircuit\core\dist\index.js:66353:10)
    at runRenderPhase (E:\project\tscircuit\metal-touch-panel\node_modules\@tscircuit\core\dist\index.js:831:24)
    at runRenderCycle (E:\project\tscircuit\metal-touch-panel\node_modules\@tscircuit\core\dist\index.js:780:12)
    at render (E:\project\tscircuit\metal-touch-panel\node_modules\@tscircuit\core\dist\index.js:68577:16)
    at generateCircuitJson (E:\project\tscircuit\metal-touch-panel\node_modules\@tscircuit\cli\dist\cli\main.js:167554:12)
    at async <anonymous> (E:\project\tscircuit\metal-touch-panel\node_modules\@tscircuit\cli\dist\cli\main.js:167661:28)
    at async <anonymous> (E:\project\tscircuit\metal-touch-panel\node_modules\@tscircuit\cli\dist\cli\main.js:182183:38)
    at async <anonymous> (E:\project\tscircuit\metal-touch-panel\node_modules\@tscircuit\cli\dist\cli\main.js:182305:15)
    at processTicksAndRejections (native:7:39)
Circuit JSON written to dist\index\circuit.json
<trace#99(from:U1.IN0A to:L1.pin1) /> is missing a name. Add a name prop to make the trace easier to identify.
<trace#100(from:U1.IN0B to:L1.pin2) /> is missing a name. Add a name prop to make the trace easier to identify.
<trace#101(from:C1.pin1 to:L1.pin1) /> is missing a name. Add a name prop to make the trace easier to identify.
<trace#102(from:C1.pin2 to:L1.pin2) /> is missing a name. Add a name prop to make the trace easier to identify.
<trace#119(from:U1.IN1A to:L2.pin1) /> is missing a name. Add a name prop to make the trace easier to identify.
<trace#120(from:U1.IN1B to:L2.pin2) /> is missing a name. Add a name prop to make the trace easier to identify.
<trace#121(from:C2.pin1 to:L2.pin1) /> is missing a name. Add a name prop to make the trace easier to identify.
<trace#122(from:C2.pin2 to:L2.pin2) /> is missing a name. Add a name prop to make the trace easier to identify.
<trace#139(from:U1.IN2A to:L3.pin1) /> is missing a name. Add a name prop to make the trace easier to identify.
<trace#140(from:U1.IN2B to:L3.pin2) /> is missing a name. Add a name prop to make the trace easier to identify.
Port [U1.GND] is not connected to net [GND] by a PCB trace.
<trace#141(from:C3.pin1 to:L3.pin1) /> is missing a name. Add a name prop to make the trace easier to identify.
<trace#142(from:C3.pin2 to:L3.pin2) /> is missing a name. Add a name prop to make the trace easier to identify.
<trace#159(from:U1.IN3A to:L4.pin1) /> is missing a name. Add a name prop to make the trace easier to identify.
<trace#160(from:U1.IN3B to:L4.pin2) /> is missing a name. Add a name prop to make the trace easier to identify.
<trace#161(from:C4.pin1 to:L4.pin1) /> is missing a name. Add a name prop to make the trace easier to identify.
<trace#162(from:C4.pin2 to:L4.pin2) /> is missing a name. Add a name prop to make the trace easier to identify.
<trace#178(from:U1.SCL to:J1.pin4) /> is missing a name. Add a name prop to make the trace easier to identify.
<trace#179(from:U1.SDA to:J1.pin3) /> is missing a name. Add a name prop to make the trace easier to identify.
<trace#180(from:R1.pin2 to:U1.SCL) /> is missing a name. Add a name prop to make the trace easier to identify.
<trace#181(from:R2.pin2 to:U1.SDA) /> is missing a name. Add a name prop to make the trace easier to identify.
<trace#182(from:U1.INTB to:J1.pin5) /> is missing a name. Add a name prop to make the trace easier to identify.
No <schematicsheet> was found. Add a <schematicsheet> to define the schematic drawing area.
L1 has no courtyard
L2 has no courtyard
L3 has no courtyard
L4 has no courtyard
All pins on U1 are underspecified (no pinAttributes set)
U1 has no pin with requires_power=true
Port [U1.EP] is not connected to net [GND] by a PCB trace.
U1 has no pin with requires_ground=true
Port [U1.CLKIN] is not connected to net [GND] by a PCB trace.
Port [U1.ADDR] is not connected to net [GND] by a PCB trace.
Port [U1.SD] is not connected to net [GND] by a PCB trace.
Port [C5.pin2] is not connected to net [GND] by a PCB trace.
Port [C6.pin2] is not connected to net [GND] by a PCB trace.
Port [J1.pin2] is not connected to net [GND] by a PCB trace.
Port [U1.VDD] is not connected to net [V3V3] by a PCB trace.
Port [C5.pin1] is not connected to net [V3V3] by a PCB trace.
Port [C6.pin1] is not connected to net [V3V3] by a PCB trace.
Port [R1.pin1] is not connected to net [V3V3] by a PCB trace.
Port [R2.pin1] is not connected to net [V3V3] by a PCB trace.
Port [J1.pin1] is not connected to net [V3V3] by a PCB trace.
Ports [U1.SCL, J1.pin4] are not connected together through the same net.
Ports [U1.SDA, J1.pin3] are not connected together through the same net.
Ports [R1.pin2, U1.SCL] are not connected together through the same net.
Ports [R2.pin2, U1.SDA] are not connected together through the same net.
Ports [U1.INTB, J1.pin5] are not connected together through the same net.
Trace [U1.SCL to J1.pin4] is not connected (it has no PCB trace)
Trace [U1.SDA to J1.pin3] is not connected (it has no PCB trace)
Trace [R1.pin2 to U1.SCL] is not connected (it has no PCB trace)
Trace [R2.pin2 to U1.SDA] is not connected (it has no PCB trace)
Trace [U1.INTB to J1.pin5] is not connected (it has no PCB trace)
Generating preview images...
[index] Generating PCB PNG...
[index] Written pcb.png
[index] Generating schematic PNG...
[index] Written schematic.png

Build complete
  Circuits  0 passed 1 failed
  Options   pcb-png, schematic-png, autorouter-debug, autorouter-timeout, autorouter-dump-srj
  Output    dist

⚠ Build completed with errors
Build exiting with code 1: circuit build errors occurred