hrithik18k/metal-touch-panel

dist/evidence/recheck-2026-09-30/props/circuit.json

PCB

Schematic

[
  {
    "type": "source_group",
    "source_group_id": "source_group_0",
    "is_subcircuit": true,
    "was_automatically_named": true,
    "subcircuit_id": "subcircuit_source_group_0"
  },
  {
    "type": "source_failed_to_create_component_error",
    "source_failed_to_create_component_error_id": "source_failed_to_create_component_error_0",
    "error_type": "source_failed_to_create_component_error",
    "message": "Could not create pcbtrace. Invalid props for pcbtrace (unnamed): route ({\"0\":{\"_errors\":[],\"route_type\":{\"_errors\":[\"Invalid literal value, expected \\\"wire\\\"\",\"Invalid literal value, expected \\\"via\\\"\",\"Invalid literal value, expected \\\"through_pad\\\"\"]},\"width\":{\"_errors\":[\"Required\",\"Required\",\"Required\",\"Required\"]},\"layer\":{\"_errors\":[\"Required\",\"Required\"]},\"from_layer\":{\"_errors\":[\"Required\",\"Required\"]},\"to_layer\":{\"_errors\":[\"Required\",\"Required\"]},\"start\":{\"_errors\":[\"Required\"]},\"end\":{\"_errors\":[\"Required\"]},\"start_layer\":{\"_errors\":[\"Required\",\"Required\"]},\"end_layer\":{\"_errors\":[\"Required\",\"Required\"]}},\"1\":{\"_errors\":[],\"route_type\":{\"_errors\":[\"Invalid literal value, expected \\\"wire\\\"\",\"Invalid literal value, expected \\\"via\\\"\",\"Invalid literal value, expected \\\"through_pad\\\"\"]},\"width\":{\"_errors\":[\"Required\",\"Required\",\"Required\",\"Required\"]},\"layer\":{\"_errors\":[\"Required\",\"Required\"]},\"from_layer\":{\"_errors\":[\"Required\",\"Required\"]},\"to_layer\":{\"_errors\":[\"Required\",\"Required\"]},\"start\":{\"_errors\":[\"Required\"]},\"end\":{\"_errors\":[\"Required\"]},\"start_layer\":{\"_errors\":[\"Required\",\"Required\"]},\"end_layer\":{\"_errors\":[\"Required\",\"Required\"]}},\"_errors\":[]}) Details: Props: {\n  \"layer\": \"top\",\n  \"thickness\": 0.2,\n  \"route\": [\n    {\n      \"x\": -4,\n      \"y\": 0\n    },\n    {\n      \"x\": 4,\n      \"y\": 0\n    }\n  ],\n  \"componentType\": \"pcbtrace\",\n  \"error\": {\n    \"componentName\": \"pcbtrace\",\n    \"originalProps\": {\n      \"layer\": \"top\",\n      \"thickness\": 0.2,\n      \"route\": \"[Circular]\"\n    },\n    \"formattedError\": {\n      \"_errors\": [],\n      \"route\": {\n        \"0\": {\n          \"_errors\": [],\n          \"route_type\": {\n            \"_errors\": [\n              \"Invalid literal value, expected \\\"wire\\\"\",\n              \"Invalid literal value, expected \\\"via\\\"\",\n              \"Invalid literal value, expected \\\"through_pad\\\"\"\n            ]\n          },\n          \"width\": {\n            \"_errors\": [\n              \"Required\",\n              \"Required\",\n              \"Required\",\n              \"Required\"\n            ]\n          },\n          \"layer\": {\n            \"_errors\": [\n              \"Required\",\n              \"Required\"\n            ]\n          },\n          \"from_layer\": {\n            \"_errors\": [\n              \"Required\",\n              \"Required\"\n            ]\n          },\n          \"to_layer\": {\n            \"_errors\": [\n              \"Required\",\n              \"Required\"\n            ]\n          },\n          \"start\": {\n            \"_errors\": [\n              \"Required\"\n            ]\n          },\n          \"end\": {\n            \"_errors\": [\n              \"Required\"\n            ]\n          },\n          \"start_layer\": {\n            \"_errors\": [\n              \"Required\",\n              \"Required\"\n            ]\n          },\n          \"end_layer\": {\n            \"_errors\": [\n              \"Required\",\n              \"Required\"\n            ]\n          }\n        },\n        \"1\": {\n          \"_errors\": [],\n          \"route_type\": {\n            \"_errors\": [\n              \"Invalid literal value, expected \\\"wire\\\"\",\n              \"Invalid literal value, expected \\\"via\\\"\",\n              \"Invalid literal value, expected \\\"through_pad\\\"\"\n            ]\n          },\n       …",
    "pcb_center": {
      "x": 0,
      "y": 0
    },
    "schematic_center": {
      "x": 0,
      "y": 0
    }
  },
  {
    "type": "source_board",
    "source_board_id": "source_board_0",
    "source_group_id": "source_group_0"
  },
  {
    "type": "schematic_group",
    "schematic_group_id": "schematic_group_0",
    "is_subcircuit": true,
    "subcircuit_id": "subcircuit_source_group_0",
    "name": "unnamed_board1",
    "center": {
      "x": 0,
      "y": 0
    },
    "width": 0,
    "height": 0,
    "schematic_component_ids": [],
    "source_group_id": "source_group_0",
    "show_as_schematic_box": false
  },
  {
    "type": "pcb_board",
    "pcb_board_id": "pcb_board_0",
    "source_board_id": "source_board_0",
    "subcircuit_id": "subcircuit_source_group_0",
    "center": {
      "x": 0,
      "y": 0
    },
    "thickness": 1.4,
    "num_layers": 2,
    "width": 20,
    "height": 20,
    "material": "fr4",
    "min_trace_width": 0.1,
    "min_via_hole_diameter": 0.2,
    "min_via_pad_diameter": 0.3,
    "min_via_hole_edge_to_via_hole_edge_clearance": 0.1,
    "min_trace_to_pad_edge_clearance": 0.1,
    "min_pad_edge_to_pad_edge_clearance": 0.1,
    "min_plated_hole_drill_edge_to_drill_edge_clearance": 0.15,
    "min_board_edge_clearance": 0.2
  },
  {
    "type": "source_project_metadata",
    "source_filesystem_md5_hash": "6e0e04cdd399752c46067c998f656281"
  }
]