abse/smartwatch-v1-pcb
Routed bare ESP32-S3 smartwatch with SDR PSRAM, touch AMOLED, Qi receiver and compact/exploded 39 × 50.5 × 14.5 mm provisional assembly.
- Version
- 0.2.0
- License
- unset
- Stars
- 0
reports/esp32/pin-audit.json
{
"sourceSha256": "7e67c63a8817464e3e07a7f916e3672202979fbfb74d7204fb756085eb694ae2",
"checkedAt": "2026-10-10T19:01:29.526Z",
"checkedPins": 252,
"failures": [],
"checked": [
{
"ref": "L1",
"pin": 1,
"expected": "SW_NODE1",
"actual": [
"SW_NODE1"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "L1",
"pin": 2,
"expected": "SW_NODE2",
"actual": [
"SW_NODE2"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U2",
"pin": 1,
"expected": "GND",
"actual": [
"GND"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U2",
"pin": 4,
"expected": "IMU_INT",
"actual": [
"IMU_INT"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U2",
"pin": 5,
"expected": "V3V3",
"actual": [
"V3V3"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U2",
"pin": 6,
"expected": "GND",
"actual": [
"GND"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U2",
"pin": 7,
"expected": "GND",
"actual": [
"GND"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U2",
"pin": 8,
"expected": "V3V3",
"actual": [
"V3V3"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U2",
"pin": 12,
"expected": "V3V3",
"actual": [
"V3V3"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U2",
"pin": 13,
"expected": "SCL",
"actual": [
"SCL"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U2",
"pin": 14,
"expected": "SDA",
"actual": [
"SDA"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U3",
"pin": 1,
"expected": "SCL",
"actual": [
"SCL"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U3",
"pin": 3,
"expected": "V3V3",
"actual": [
"V3V3"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U3",
"pin": 4,
"expected": "SDA",
"actual": [
"SDA"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U3",
"pin": 5,
"expected": "MAG_CAP",
"actual": [
"MAG_CAP"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U3",
"pin": 6,
"expected": "GND",
"actual": [
"GND"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U3",
"pin": 7,
"expected": "MAG_INT",
"actual": [
"MAG_INT"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U3",
"pin": 8,
"expected": "GND",
"actual": [
"GND"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U3",
"pin": 9,
"expected": "V3V3",
"actual": [
"V3V3"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U3",
"pin": 10,
"expected": "V3V3",
"actual": [
"V3V3"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U4",
"pin": 1,
"expected": "GND",
"actual": [
"GND"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U4",
"pin": 2,
"expected": "SDA",
"actual": [
"SDA"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U4",
"pin": 3,
"expected": "ALS_INT",
"actual": [
"ALS_INT"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U4",
"pin": 4,
"expected": "GND",
"actual": [
"GND"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U4",
"pin": 5,
"expected": "SCL",
"actual": [
"SCL"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U4",
"pin": 6,
"expected": "V3V3",
"actual": [
"V3V3"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U6",
"pin": 1,
"expected": "CHARGER_TS",
"actual": [
"CHARGER_TS"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U6",
"pin": 2,
"expected": "BAT",
"actual": [
"BAT"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U6",
"pin": 3,
"expected": "BAT",
"actual": [
"BAT"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U6",
"pin": 4,
"expected": "CHARGE_CE",
"actual": [
"CHARGE_CE"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U6",
"pin": 5,
"expected": "RAW",
"actual": [
"RAW"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U6",
"pin": 6,
"expected": "GND",
"actual": [
"GND"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U6",
"pin": 7,
"expected": "PGOOD",
"actual": [
"PGOOD"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U6",
"pin": 8,
"expected": "GND",
"actual": [
"GND"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U6",
"pin": 9,
"expected": "CHG_STATUS",
"actual": [
"CHG_STATUS"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U6",
"pin": 10,
"expected": "RAW",
"actual": [
"RAW"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U6",
"pin": 11,
"expected": "RAW",
"actual": [
"RAW"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U6",
"pin": 12,
"expected": "ILIM",
"actual": [
"ILIM"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U6",
"pin": 13,
"expected": "INPUT_5V",
"actual": [
"INPUT_5V"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U6",
"pin": 16,
"expected": "ISET",
"actual": [
"ISET"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U6",
"pin": 17,
"expected": "GND",
"actual": [
"GND"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U7",
"pin": 1,
"expected": "RAW",
"actual": [
"RAW"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U7",
"pin": 2,
"expected": "GND",
"actual": [
"GND"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U7",
"pin": 3,
"expected": "GND",
"actual": [
"GND"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U7",
"pin": 4,
"expected": "FB_SYS",
"actual": [
"FB_SYS"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U7",
"pin": 5,
"expected": "SYS_PG",
"actual": [
"SYS_PG"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U7",
"pin": 6,
"expected": "VSYS",
"actual": [
"VSYS"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U7",
"pin": 7,
"expected": "SW_NODE2",
"actual": [
"SW_NODE2"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U7",
"pin": 8,
"expected": "GND",
"actual": [
"GND"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U7",
"pin": 9,
"expected": "SW_NODE1",
"actual": [
"SW_NODE1"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U7",
"pin": 10,
"expected": "RAW",
"actual": [
"RAW"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U8",
"pin": 1,
"expected": "GND",
"actual": [
"GND"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U8",
"pin": 2,
"expected": "BAT",
"actual": [
"BAT"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U8",
"pin": 3,
"expected": "BAT",
"actual": [
"BAT"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U8",
"pin": 4,
"expected": "GND",
"actual": [
"GND"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U8",
"pin": 5,
"expected": "GAUGE_INT",
"actual": [
"GAUGE_INT"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U8",
"pin": 6,
"expected": "GND",
"actual": [
"GND"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U8",
"pin": 7,
"expected": "SCL",
"actual": [
"SCL"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U8",
"pin": 8,
"expected": "SDA",
"actual": [
"SDA"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U8",
"pin": 9,
"expected": "GND",
"actual": [
"GND"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U9",
"pin": 1,
"expected": "HAP_REG",
"actual": [
"HAP_REG"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U9",
"pin": 2,
"expected": "SCL",
"actual": [
"SCL"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U9",
"pin": 3,
"expected": "SDA",
"actual": [
"SDA"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U9",
"pin": 4,
"expected": "GND",
"actual": [
"GND"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U9",
"pin": 5,
"expected": "HAPTIC_EN",
"actual": [
"HAPTIC_EN"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U9",
"pin": 6,
"expected": "V3V3",
"actual": [
"V3V3"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U9",
"pin": 7,
"expected": "MOTOR_P",
"actual": [
"MOTOR_P"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U9",
"pin": 8,
"expected": "GND",
"actual": [
"GND"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U9",
"pin": 9,
"expected": "MOTOR_N",
"actual": [
"MOTOR_N"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U9",
"pin": 10,
"expected": "V3V3",
"actual": [
"V3V3"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U10",
"pin": 1,
"expected": "VSYS",
"actual": [
"VSYS"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U10",
"pin": 2,
"expected": "GND",
"actual": [
"GND"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U10",
"pin": 3,
"expected": "VSYS",
"actual": [
"VSYS"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U10",
"pin": 5,
"expected": "V3V3",
"actual": [
"V3V3"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U11",
"pin": 1,
"expected": "VSYS",
"actual": [
"VSYS"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U11",
"pin": 2,
"expected": "GND",
"actual": [
"GND"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U11",
"pin": 3,
"expected": "VSYS",
"actual": [
"VSYS"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U11",
"pin": 5,
"expected": "V1V8",
"actual": [
"V1V8"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U12",
"pin": 1,
"expected": "VSYS",
"actual": [
"VSYS"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U12",
"pin": 2,
"expected": "GND",
"actual": [
"GND"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U12",
"pin": 3,
"expected": "DISP_EN",
"actual": [
"DISP_EN"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U12",
"pin": 4,
"expected": "FB_LCD",
"actual": [
"FB_LCD"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U12",
"pin": 5,
"expected": "OLED_VDD",
"actual": [
"OLED_VDD"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U14",
"pin": 1,
"expected": "SCL",
"actual": [
"SCL"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U14",
"pin": 2,
"expected": "PPG_INT",
"actual": [
"PPG_INT"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U14",
"pin": 3,
"expected": "GND",
"actual": [
"GND"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U14",
"pin": 4,
"expected": "V3V3",
"actual": [
"V3V3"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U14",
"pin": 5,
"expected": "V1V8",
"actual": [
"V1V8"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U14",
"pin": 6,
"expected": "GND",
"actual": [
"GND"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U14",
"pin": 8,
"expected": "PPG_REF",
"actual": [
"PPG_REF"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U14",
"pin": 10,
"expected": "V1V8",
"actual": [
"V1V8"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U14",
"pin": 11,
"expected": "GND",
"actual": [
"GND"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U14",
"pin": 12,
"expected": "SDA",
"actual": [
"SDA"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U14",
"pin": 13,
"expected": "V3V3",
"actual": [
"V3V3"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U17",
"pin": 1,
"expected": "TEMP_OK",
"actual": [
"TEMP_OK"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U17",
"pin": 2,
"expected": "GND",
"actual": [
"GND"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U17",
"pin": 3,
"expected": "COLD_REF",
"actual": [
"COLD_REF"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U17",
"pin": 4,
"expected": "NTC",
"actual": [
"NTC"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U17",
"pin": 5,
"expected": "V3V3",
"actual": [
"V3V3"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U18",
"pin": 1,
"expected": "TEMP_OK",
"actual": [
"TEMP_OK"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U18",
"pin": 2,
"expected": "GND",
"actual": [
"GND"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U18",
"pin": 3,
"expected": "NTC",
"actual": [
"NTC"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U18",
"pin": 4,
"expected": "HOT_REF",
"actual": [
"HOT_REF"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U18",
"pin": 5,
"expected": "V3V3",
"actual": [
"V3V3"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "Q3",
"pin": 1,
"expected": "TEMP_OK",
"actual": [
"TEMP_OK"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "Q3",
"pin": 2,
"expected": "GND",
"actual": [
"GND"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "Q3",
"pin": 3,
"expected": "CHARGE_CE",
"actual": [
"CHARGE_CE"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "Q4",
"pin": 1,
"expected": "CHARGE_INHIBIT",
"actual": [
"CHARGE_INHIBIT"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "Q4",
"pin": 2,
"expected": "GND",
"actual": [
"GND"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "Q4",
"pin": 3,
"expected": "TEMP_OK",
"actual": [
"TEMP_OK"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "D1",
"pin": 1,
"expected": "GND",
"actual": [
"GND"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "D1",
"pin": 2,
"expected": "DOCK_5V",
"actual": [
"DOCK_5V"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "J1",
"pin": 1,
"expected": "OLED_D3",
"actual": [
"OLED_D3"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "J1",
"pin": 2,
"expected": "OLED_D2",
"actual": [
"OLED_D2"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "J1",
"pin": 3,
"expected": "OLED_D0",
"actual": [
"OLED_D0"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "J1",
"pin": 4,
"expected": "OLED_RST",
"actual": [
"OLED_RST"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "J1",
"pin": 5,
"expected": "OLED_CLK",
"actual": [
"OLED_CLK"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "J1",
"pin": 6,
"expected": "OLED_D1",
"actual": [
"OLED_D1"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "J1",
"pin": 7,
"expected": "OLED_CS",
"actual": [
"OLED_CS"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "J1",
"pin": 8,
"expected": "GND",
"actual": [
"GND"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "J1",
"pin": 9,
"expected": "OLED_TE",
"actual": [
"OLED_TE"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "J1",
"pin": 10,
"expected": "OLED_VDD",
"actual": [
"OLED_VDD"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "J1",
"pin": 11,
"expected": "OLED_BOOST_EN",
"actual": [
"OLED_BOOST_EN"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "J1",
"pin": 13,
"expected": "V3V3",
"actual": [
"V3V3"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "J1",
"pin": 14,
"expected": "TP_INT",
"actual": [
"TP_INT"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "J1",
"pin": 15,
"expected": "SCL",
"actual": [
"SCL"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "J1",
"pin": 16,
"expected": "SDA",
"actual": [
"SDA"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "J1",
"pin": 17,
"expected": "TP_RST",
"actual": [
"TP_RST"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "J1",
"pin": 19,
"expected": "GND",
"actual": [
"GND"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "J1",
"pin": 20,
"expected": "GND",
"actual": [
"GND"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "J1",
"pin": 21,
"expected": "GND",
"actual": [
"GND"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "SW1",
"pin": 1,
"expected": "KEY",
"actual": [
"KEY"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "SW1",
"pin": 2,
"expected": "GND",
"actual": [
"GND"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "R36",
"pin": 1,
"expected": "V3V3",
"actual": [
"V3V3"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "R36",
"pin": 2,
"expected": "KEY",
"actual": [
"KEY"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "R45",
"pin": 1,
"expected": "UART_TX",
"actual": [
"UART_TX"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "R45",
"pin": 2,
"expected": "UART_CABLE_TX",
"actual": [
"UART_CABLE_TX"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "J5",
"pin": 1,
"expected": "UART_RX",
"actual": [
"UART_RX"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "J5",
"pin": 2,
"expected": "GND",
"actual": [
"GND"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "J5",
"pin": 3,
"expected": "UART_CABLE_TX",
"actual": [
"UART_CABLE_TX"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "J5",
"pin": 4,
"expected": "GND",
"actual": [
"GND"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "J5",
"pin": 5,
"expected": "GND",
"actual": [
"GND"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U1",
"pin": 1,
"expected": "RF_CHIP",
"actual": [
"RF_CHIP"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U1",
"pin": 2,
"expected": "VDD_RF",
"actual": [
"VDD_RF"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U1",
"pin": 3,
"expected": "VDD_RF",
"actual": [
"VDD_RF"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U1",
"pin": 4,
"expected": "MCU_EN",
"actual": [
"MCU_EN"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U1",
"pin": 5,
"expected": "BOOT",
"actual": [
"BOOT"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U1",
"pin": 6,
"expected": "IMU_INT",
"actual": [
"IMU_INT"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U1",
"pin": 7,
"expected": "PPG_INT",
"actual": [
"PPG_INT"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U1",
"pin": 9,
"expected": "KEY",
"actual": [
"KEY"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U1",
"pin": 10,
"expected": "CHARGE_INHIBIT",
"actual": [
"CHARGE_INHIBIT"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U1",
"pin": 11,
"expected": "SCL",
"actual": [
"SCL"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U1",
"pin": 12,
"expected": "SDA",
"actual": [
"SDA"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U1",
"pin": 13,
"expected": "TP_RST",
"actual": [
"TP_RST"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U1",
"pin": 14,
"expected": "TP_INT",
"actual": [
"TP_INT"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U1",
"pin": 15,
"expected": "OLED_CS",
"actual": [
"OLED_CS"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U1",
"pin": 16,
"expected": "OLED_D0",
"actual": [
"OLED_D0"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U1",
"pin": 17,
"expected": "OLED_CLK",
"actual": [
"OLED_CLK"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U1",
"pin": 18,
"expected": "OLED_D1",
"actual": [
"OLED_D1"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U1",
"pin": 19,
"expected": "OLED_RST",
"actual": [
"OLED_RST"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U1",
"pin": 20,
"expected": "V3V3",
"actual": [
"V3V3"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U1",
"pin": 23,
"expected": "OLED_D2",
"actual": [
"OLED_D2"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U1",
"pin": 24,
"expected": "DISP_EN",
"actual": [
"DISP_EN"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U1",
"pin": 27,
"expected": "OLED_D3",
"actual": [
"OLED_D3"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U1",
"pin": 28,
"expected": "RAM_CS",
"actual": [
"RAM_CS"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U1",
"pin": 29,
"expected": "V3V3",
"actual": [
"V3V3"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U1",
"pin": 30,
"expected": "MEM_D3",
"actual": [
"MEM_D3"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U1",
"pin": 31,
"expected": "MEM_D2",
"actual": [
"MEM_D2"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U1",
"pin": 32,
"expected": "FLASH_CS",
"actual": [
"FLASH_CS"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U1",
"pin": 33,
"expected": "MEM_CLK",
"actual": [
"MEM_CLK"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U1",
"pin": 34,
"expected": "MEM_D1",
"actual": [
"MEM_D1"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U1",
"pin": 35,
"expected": "MEM_D0",
"actual": [
"MEM_D0"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U1",
"pin": 38,
"expected": "HAPTIC_EN",
"actual": [
"HAPTIC_EN"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U1",
"pin": 40,
"expected": "GAUGE_INT",
"actual": [
"GAUGE_INT"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U1",
"pin": 41,
"expected": "CHG_STATUS",
"actual": [
"CHG_STATUS"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U1",
"pin": 42,
"expected": "PGOOD",
"actual": [
"PGOOD"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U1",
"pin": 43,
"expected": "MAG_INT",
"actual": [
"MAG_INT"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U1",
"pin": 44,
"expected": "ALS_INT",
"actual": [
"ALS_INT"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U1",
"pin": 46,
"expected": "V3V3",
"actual": [
"V3V3"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U1",
"pin": 47,
"expected": "OLED_TE",
"actual": [
"OLED_TE"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U1",
"pin": 48,
"expected": "OLED_BOOST_EN",
"actual": [
"OLED_BOOST_EN"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U1",
"pin": 49,
"expected": "UART_TX",
"actual": [
"UART_TX"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U1",
"pin": 50,
"expected": "UART_RX",
"actual": [
"UART_RX"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U1",
"pin": 51,
"expected": "STRAP45",
"actual": [
"STRAP45"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U1",
"pin": 52,
"expected": "STRAP46",
"actual": [
"STRAP46"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U1",
"pin": 53,
"expected": "XTAL_N",
"actual": [
"XTAL_N"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U1",
"pin": 54,
"expected": "XTAL_P_MCU",
"actual": [
"XTAL_P_MCU"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U1",
"pin": 55,
"expected": "V3V3",
"actual": [
"V3V3"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U1",
"pin": 56,
"expected": "V3V3",
"actual": [
"V3V3"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U1",
"pin": 57,
"expected": "GND",
"actual": [
"GND"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U15",
"pin": 1,
"expected": "FLASH_CS",
"actual": [
"FLASH_CS"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U15",
"pin": 2,
"expected": "MEM_D1",
"actual": [
"MEM_D1"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U15",
"pin": 3,
"expected": "MEM_D2",
"actual": [
"MEM_D2"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U15",
"pin": 4,
"expected": "GND",
"actual": [
"GND"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U15",
"pin": 5,
"expected": "MEM_D0",
"actual": [
"MEM_D0"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U15",
"pin": 6,
"expected": "MEM_CLK",
"actual": [
"MEM_CLK"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U15",
"pin": 7,
"expected": "MEM_D3",
"actual": [
"MEM_D3"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U15",
"pin": 8,
"expected": "V3V3",
"actual": [
"V3V3"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U19",
"pin": 1,
"expected": "RAM_CS",
"actual": [
"RAM_CS"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U19",
"pin": 2,
"expected": "MEM_D1",
"actual": [
"MEM_D1"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U19",
"pin": 3,
"expected": "MEM_D2",
"actual": [
"MEM_D2"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U19",
"pin": 4,
"expected": "GND",
"actual": [
"GND"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U19",
"pin": 5,
"expected": "MEM_D0",
"actual": [
"MEM_D0"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U19",
"pin": 6,
"expected": "MEM_CLK",
"actual": [
"MEM_CLK"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U19",
"pin": 7,
"expected": "MEM_D3",
"actual": [
"MEM_D3"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U19",
"pin": 8,
"expected": "V3V3",
"actual": [
"V3V3"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "X1",
"pin": 1,
"expected": "XTAL_P",
"actual": [
"XTAL_P"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "X1",
"pin": 2,
"expected": "GND",
"actual": [
"GND"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "X1",
"pin": 3,
"expected": "XTAL_N",
"actual": [
"XTAL_N"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "X1",
"pin": 4,
"expected": "GND",
"actual": [
"GND"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "A1",
"pin": 1,
"expected": "RF_ANT",
"actual": [
"RF_ANT"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U20",
"pin": 1,
"expected": "GND",
"actual": [
"GND"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U20",
"pin": 2,
"expected": "QI_AC1",
"actual": [
"QI_AC1"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U20",
"pin": 3,
"expected": "QI_BOOT1",
"actual": [
"QI_BOOT1"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U20",
"pin": 4,
"expected": "QI_5V",
"actual": [
"QI_5V"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U20",
"pin": 5,
"expected": "QI_CLAMP1",
"actual": [
"QI_CLAMP1"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U20",
"pin": 6,
"expected": "QI_COM1",
"actual": [
"QI_COM1"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U20",
"pin": 9,
"expected": "GND",
"actual": [
"GND"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U20",
"pin": 10,
"expected": "GND",
"actual": [
"GND"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U20",
"pin": 11,
"expected": "GND",
"actual": [
"GND"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U20",
"pin": 12,
"expected": "QI_ILIM",
"actual": [
"QI_ILIM"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U20",
"pin": 13,
"expected": "QI_TS",
"actual": [
"QI_TS"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U20",
"pin": 14,
"expected": "QI_FOD",
"actual": [
"QI_FOD"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U20",
"pin": 15,
"expected": "QI_COM2",
"actual": [
"QI_COM2"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U20",
"pin": 16,
"expected": "QI_CLAMP2",
"actual": [
"QI_CLAMP2"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U20",
"pin": 17,
"expected": "QI_BOOT2",
"actual": [
"QI_BOOT2"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U20",
"pin": 18,
"expected": "QI_RECT",
"actual": [
"QI_RECT"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U20",
"pin": 19,
"expected": "QI_AC2",
"actual": [
"QI_AC2"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U20",
"pin": 20,
"expected": "GND",
"actual": [
"GND"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "U20",
"pin": 21,
"expected": "GND",
"actual": [
"GND"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "SW2",
"pin": 1,
"expected": "BOOT",
"actual": [
"BOOT"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "SW2",
"pin": 2,
"expected": "GND",
"actual": [
"GND"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "SW2",
"pin": 3,
"expected": "BOOT",
"actual": [
"BOOT"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "SW2",
"pin": 4,
"expected": "GND",
"actual": [
"GND"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "SW2",
"pin": 5,
"expected": "GND",
"actual": [
"GND"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "SW3",
"pin": 1,
"expected": "MCU_EN",
"actual": [
"MCU_EN"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "SW3",
"pin": 2,
"expected": "GND",
"actual": [
"GND"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "SW3",
"pin": 3,
"expected": "MCU_EN",
"actual": [
"MCU_EN"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "SW3",
"pin": 4,
"expected": "GND",
"actual": [
"GND"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "SW3",
"pin": 5,
"expected": "GND",
"actual": [
"GND"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "J3",
"pin": 1,
"expected": "BAT",
"actual": [
"BAT"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "J3",
"pin": 2,
"expected": "GND",
"actual": [
"GND"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "J6",
"pin": 1,
"expected": "QI_COIL1",
"actual": [
"QI_COIL1"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "J6",
"pin": 2,
"expected": "QI_AC2",
"actual": [
"QI_AC2"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "J7",
"pin": 1,
"expected": "NTC",
"actual": [
"NTC"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "J7",
"pin": 2,
"expected": "GND",
"actual": [
"GND"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "J8",
"pin": 1,
"expected": "QI_TS",
"actual": [
"QI_TS"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "J8",
"pin": 2,
"expected": "GND",
"actual": [
"GND"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "D2",
"pin": 1,
"expected": "INPUT_5V",
"actual": [
"INPUT_5V"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "D2",
"pin": 2,
"expected": "DOCK_5V",
"actual": [
"DOCK_5V"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "D3",
"pin": 1,
"expected": "INPUT_5V",
"actual": [
"INPUT_5V"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
},
{
"ref": "D3",
"pin": 2,
"expected": "QI_5V",
"actual": [
"QI_5V"
],
"pcbPorts": 1,
"schematicPorts": 0,
"pads": 1
}
],
"hasSchematic": false,
"note": "Independent numbered-pin source/PCB-pad association audit. Schematic ports checked only when present. Copper continuity and unintended shorts are separate checks."
}
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