README.md
# PCBGolf modular engineering checkpoint
This is an **incomplete engineering preview**, derived from comma.ai's [PCBGolf](https://github.com/commaai/PCBGolf) challenge circuit. It is worth reviewing for the compact locally routed modules and the assembly experiments. It is not a finished competition entry or a fabrication release.
## TSX assembly preview (v0.0.6)
Open **3D** on `assembly-main.tsx` to inspect the current partial geometry. The default view shows only seven separate PCB models using `assembly.subassembly`: five USB carriers, the native MCU coupon, and CH1_SBU2. Connector bodies are hidden. `assembly-boards.tsx` and `assembly-connectors.tsx` keep the PCB and connector objects distinct. Each native mesh stays in its original local coordinates; `assembly-assets/pose.json` supplies independently editable XYZ positions and rotations. The PCB transforms preserve their positions in the frozen native witness; its complete partial geometry, including hidden connectors, bounds 26.114 × 17.694 × 8.126 mm. Purple is MCU, green is SBU, blue is a USB carrier, gray is a USB drawing proxy and amber is the DC receiver.
This is the final representation of the **current partial state**, with 18 populated electronics references. It is not a completed design. The known fixed-layout cost lower bound remains **14,104.923**, including seven MCU vias and two copper layers. External wiring, remaining circuits, supports and qualified solder/tool access are missing. Mesh tessellation is for display; native STEP remains authoritative for geometry checks.
**Native tilted `<board>` test:** `board-rotation-repro.tsx` creates two distinct PCB records, but `cadModel` is not a supported board prop and therefore does not position or rotate it. A board mounted to an X-facing motor explicitly throws “rotated PCB boards are not yet supported.” This was reproduced with core 0.0.2132 and props 0.0.700; the [assembly documentation](https://docs.tscircuit.com/guides/advanced-assembly) also describes planar PCB anchors. The working 3D view therefore uses separate native PCB models as assembly subassemblies. These CAD objects do not create electrical boards or route interconnections. Electrical PCB previews remain separate in the ten `.circuit.json` files.
Run `npm install`, then `npx tsci build assembly-main.tsx` or `npx tsci dev`. The source uses local GLB imports; uploaded prebuilt previews resolve those assets to version-pinned registry URLs. `assembly-validation.json` records native sources, hashes and placement parity; `board-rotation-results.json` records the tests.
## What is included
- `core19.circuit.json`: converted preview of a native 18 × 10 × 0.4 mm two-layer MCU/IO core. There are 19 populated components, 118 canonical pins, 62 external copper lands and 22 through vias. Fresh native KiCad DRC reports zero physical errors and zero opens, with 20 disclosed library/courtyard warnings. The local populated STEP box is 18 × 10 × 2.38 mm. The preview also shows the unpopulated XP_CORE boundary lands.
- Eight `chN_sbuM.circuit.json` files: native 7.6 × 6.4 × 0.4 mm two-layer SBU islands. Each retains 10 canonical components and 25 canonical pins, plus boundary copper lands. Each has zero vias and one modeled ground wire. The bare board has one deliberate ground split; the wire closes it in the native/actual-pad validator. The preview does not model that wire. All 80 references and 200 canonical pins match the revised schematic. Forty external joins across the eight islands remain absent.
- Seven archives under `native/`: portable native KiCad sources, local STEP exports, full revised schematic and validation artifacts. All 259 references, 266 nets and 1,028 pin nodes in the schematic are retained. Fresh native ERC and migration audit pass. R4 is the corrected 31.3 kΩ ordering code; sixteen LED series resistors are 680 Ω. SHA-256 manifests are included.
- `resumed-assembly.png`: preview of the partial DC/USB/carrier placement containing only two SBU islands (20 electronics references). Native STEP files are inside the assembly archives.
Download and extract **all seven** archives into the **same folder** to retain the portable relative library/model paths: [core](https://registry-api.tscircuit.com/package_files/download?package_name_with_version=0hmX%2Fpcbgolf-modular-checkpoint%400.0.6&file_path=native%2Fcore.zip), [islands](https://registry-api.tscircuit.com/package_files/download?package_name_with_version=0hmX%2Fpcbgolf-modular-checkpoint%400.0.6&file_path=native%2Fislands.zip), [schematic](https://registry-api.tscircuit.com/package_files/download?package_name_with_version=0hmX%2Fpcbgolf-modular-checkpoint%400.0.6&file_path=native%2Fschematic.zip), [model dependencies](https://registry-api.tscircuit.com/package_files/download?package_name_with_version=0hmX%2Fpcbgolf-modular-checkpoint%400.0.6&file_path=native%2Fmodel-dependencies.zip), [partial assembly](https://registry-api.tscircuit.com/package_files/download?package_name_with_version=0hmX%2Fpcbgolf-modular-checkpoint%400.0.6&file_path=native%2Fpartial-assembly.zip), [partial assembly with cables](https://registry-api.tscircuit.com/package_files/download?package_name_with_version=0hmX%2Fpcbgolf-modular-checkpoint%400.0.6&file_path=native%2Fpartial-assembly-cables.zip), [validation](https://registry-api.tscircuit.com/package_files/download?package_name_with_version=0hmX%2Fpcbgolf-modular-checkpoint%400.0.6&file_path=native%2Fvalidation.zip). Open `work/candidates/resume_electrical/compact_singles_usb2517_r4_led680/full.kicad_sch` for the full revised schematic.
## How to interpret the preview
The Circuit JSON files were generated using `kicad-to-circuit-json`; they are review previews. Native KiCad copper and native exported STEP geometry remain authoritative. The converter sanitizes net names, so original native labels were restored only after checking that the mapping is bijective. Imported copper pours also require their missing `source_net_id` links, which are assigned from verified native net names. Independent pcbnew checks confirm every electrical reference, value and pad/net membership, two copper layers and via count. Non-electrical blank model-anchor pads are omitted. This does not establish geometry equivalence: pad shape approximations, grouping of copper routes/pours and generic preview component bodies can differ. The web schematic preview is not the authoritative six-sheet schematic; use the native files in the ZIP.
All ten previews build and pass `tsci check shorts`. The CLI source-netlist check cannot consume these prebuilt JSON arrays; the independent native pin/net audit supplies that evidence. The placement heuristic flags XP_CORE against U3/U17 because 62 separated copper lands share one aggregate footprint rectangle, and flags three capacitor orientation suggestions. Some boundary lands intentionally overlap same-net IC lead copper. Their actual copper is outside conservative front component bodies, with gaps as small as **0.025 mm** at U17 and **0.10 mm** at U3 CAN2_RX. These tiny gaps do not qualify wire attachment, solder access, assembly tolerance or component clearance for a finished product.
## Smaller MCU carrier experiment
`st7p70_mcu.circuit.json` previews a separate **7.70 × 7.70 × 0.4 mm** native carrier using the ST DS12288 Rev6 Figure 57 land pattern. It holds U3, five original 100 nF capacitors and the original BTN/NRST resistors: **eight canonical references and 63 pins**, plus three receiving lands. Native local copper closes with **seven vias**, zero errors, zero opens and eight disclosed library/courtyard warnings. The original 19-reference core remains a separate validated donor; its other eleven supports are absent from this carrier. There are no component substitutions in this experiment.
The copper-inclusive populated STEP measures **7.70 × 7.70 × 1.63 mm**. It fits the actual connector/cable cage while retaining CH1_SBU2, with **0.376 mm minimum modeled foreign clearance** and an unchanged **3,754.923 mm³** partial envelope. It replaces CH1_SBU1, which still needs another assembled location. The fit witness contains only **18 populated electronics references**. Even its partial envelope plus seven known vias and the two-layer penalty costs **14,104.923**, above the 13,858 target before the remaining circuitry.
**42 external nets remain unwired.** Receiving joints, oscillator/analog supply support, expander, full harness, debug/SD placement and all remaining system components are absent. Seven support-body models are generic nominal geometry with unverified original-part maximum dimensions. Solder/tool access, paste/stencil, via-in-pad process, manufacturing tolerance, supplier approval and physical assembly are unqualified. This is an actual native placement lead, not a complete MCU system or a winning entry.
Extract these optional archives alongside the seven base archives: [MCU source](https://registry-api.tscircuit.com/package_files/download?package_name_with_version=0hmX%2Fpcbgolf-modular-checkpoint%400.0.6&file_path=native%2Fmcu-fit-source.zip), [fitted assembly](https://registry-api.tscircuit.com/package_files/download?package_name_with_version=0hmX%2Fpcbgolf-modular-checkpoint%400.0.6&file_path=native%2Fmcu-fit-assembly.zip), [fitted assembly with cables](https://registry-api.tscircuit.com/package_files/download?package_name_with_version=0hmX%2Fpcbgolf-modular-checkpoint%400.0.6&file_path=native%2Fmcu-fit-cables.zip). The source archive includes exact hashes, original canonical graph, endpoint/partition contracts, primary drawing links and manufacturing review.
## Work remaining
The **partial** assembly box measures 26.11415 × 17.69398 × 8.12643 mm = **3,754.923 mm³**. It contains only 20 of 251 populated electronics references. That volume is not a complete assembly score and does not establish a leaderboard result. The routed core is not fitted into it. Tested finite core, buck, SD and further-island placements failed; they are not global impossibility proofs.
Interboard wiring, support-board rebuilding, remaining placement/routing, receiving solder joints, cable/assembly tolerance and solder access qualification remain unfinished. The partition's 151 functional interboard conductors are only a minimum; USB returns and harness geometry need further work. Firmware migration is unbuilt and untested. Connector retention, current/thermal behavior, signal integrity, manufacturing tolerances, LED drive/brightness and physical assembly are not bench qualified. Five USB connections and the usable 0.1-inch debug footprint remain required.
## Attribution and provenance
Original circuit: comma.ai PCBGolf, upstream revision `d0fd5a71087e3e10a49610f8c3e89912b4d20d77`. The original donor checkpoint comes from local Git revision `5e48d4d`; the smaller carrier is a subsequent hash-bound experiment included in this release. Native library models retain their source attribution and KiCad library license in the ZIP. No blanket license for the upstream circuit or vendor models is asserted by this package; `UNLICENSED` avoids assigning one. The engineering files are published for review at the user's request.
