README.md
**v1.3.2 packaging recovery:** complete matching v1.3.1 source and checked board artifacts restored; large 3D assets are losslessly split for registry transport. This does not create a new hardware qualification. See [recovery notes](docs/publication-recovery-v1.3.2.md).
# Muse Voice Remote
A rechargeable Wi-Fi voice remote designed in tscircuit, with a **bare
ESP32-S3R8 QFN chip**, two ICS-43434 microphones, TALK, hardware microphone
privacy, display, speaker, vibration and status LEDs. The exact display is
**ER-TFT028A2-4, 2.8-inch IPS, no touch, 320 × 240 landscape**.
The revised PCB has **155 components on TOP, from 56 JLCPCB imports**. Each
populated component retains its original supplier footprint and OBJ/STEP CAD
references. Stock evidence covers every selected PCB MPN at the recorded time;
stock is not reserved. No custom electronic footprints or module substitutes
are used. U1 has 8 MB in-package PSRAM, with separate 8 MB flash, crystal and RF
circuitry.
The **v1.3.1 prototype PCB/PCBA manufacturing handoff is verified**: all 21 tests
pass, native and factory DRC are clean, and BOM/CPL, artwork and archive hashes
are cross-checked. Physical device qualification remains pending. Earlier v1.2.0–v1.2.1 review releases are not orderable
baselines. Hardware operation, enclosure fit, external battery/transducers and
MUSE integration still require physical verification. No functioning firmware
or connected Meta MUSE integration is present.
## Manufacturing files
[Download the complete v1.3.1 handoff](manufacturing/MuseVoiceRemote-fabrication-v1.3.1.zip).
Upload the [Gerber ZIP](manufacturing/MuseVoiceRemote-Gerbers-JLCPCB-v1.3.1.zip) for PCB fabrication and the [BOM](manufacturing/BOM-JLCPCB.csv) / [TOP CPL](manufacturing/CPL-JLCPCB.csv) for assembly. Apply the quoted stackup, controlled impedance and nineteen filled/capped thermal-hole requirements below.
The complete handoff contains:
- Four-layer copper, masks, silkscreen, outline and paste Gerbers.
- Separate metric PTH/NPTH drill files and drill maps.
- JLCPCB BOM and top-only CPL, cross-checked against native positions.
- Factory KiCad CAD/rules, both native DRC reports, reference map and SHA-256 list.
- Filled/capped thermal-via map and segmented exposed-pad stencil artwork.
- Fabrication and bring-up notes for the selected JLC04101H-3313 stackup.
The 66 × 48 × 1 mm PCB is specified four-layer, ENIG, black mask, white silk,
0.15/0.15 mm track/clearance, 0.5 mm copper-edge clearance and 0.30 mm minimum via drill / 0.45 mm minimum via pad.
Layer 2 is reserved for GND. Specify resin-filled/copper-capped processing for
the nineteen exposed-pad thermal holes; keep microphone ports open. The factory
copy enlarges only the imported microphone acoustic NPTH ports from 0.40 to
0.50 mm for the manufacturer’s minimum; supplier libraries and electronic lands
remain unchanged. Controlled
50 Ω RF / 90 Ω USB requires fabricator confirmation for the specified stackup.
See [fabrication notes](docs/fabrication-notes.md) and
[engineering review](docs/design-review.md).
## Verify and open
```sh
npm ci
npm run check
npm run drc
npm run audit:research
XDG_CONFIG_HOME=/workspace/.config /usr/bin/python3 scripts/export-fabrication.py
```
`npm run check` type-checks, audits component families/values/voltages, renders
Circuit JSON and runs connectivity/import/CAD/stock/copper tests. `npm run drc`
checks retained native CAD with KiCad 9. Normal builds reuse checked routing,
with hashes rejecting stale wiring, placement or CAD. The native board is
authoritative for fabrication. tscircuit retains the real filled plane geometry,
including clearance holes, in its copper interchange.
Run `npm run dev` and open `http://localhost:8080/assembly/` for the interactive
3D assembly, exploded view and populated-PCB model. All 155 imported supplier
meshes now load, with 56 original OBJ/STEP pairs retained under `models/jlcpcb`.
Large GLB and assembly-ZIP assets use SHA-256-verified byte parts to fit the registry upload limit. The viewer assembles the original GLB bytes automatically; use **Download assembly ZIP** for the complete bundle. For a desktop viewer, run `python3 assembly/reassemble-assets.py assembly/assets.json` inside the extracted bundle to restore the original GLB files.
`dist/review.html` also includes the schematic, top assembly and parts views.
Mechanical allocations remain labelled envelopes. [3D assembly notes](docs/3d-assembly.md)
explain the native tscircuit API, exports and revised 17 mm case proposal.
[Routing notes](docs/routing.md) explain controlled rerouting; normal
builds must not repack components or regenerate native CAD over checked copper.
## Hardware and firmware requirements
| Function | Hardware |
| --- | --- |
| MCU | ESP32-S3R8 bare QFN56; external W25Q64JVSSIQ and 40 MHz crystal |
| Microphones / privacy | Two ICS-43434; DPDT cuts/grounds MIC_VDD and disables all three digital buffers |
| LCD | Hirose FH12A-50S-0.5SH(55), TLV70228 2.8 V rail, five level buffers, serial-II IM=1110 |
| Backlight | TPS61169, 40 mA nominal total, four 100 Ω ballasts, AO3401A input switch with transistor gate drive |
| Charge / main power | BQ24074RGTT; TPS63001 fixed 3.3 V buck-boost |
| Speaker / haptic | MAX98357A bridge output; regulated 3.0 V motor rail, AO3400A and SS14 flyback |
| Connectors | USB-C; side-entry 3-pin JST PA battery/NTC; two-pin JST SH speaker/motor |
Charger input defaults to USB100. Firmware may select USB500 only after host
configuration authorizes it and must implement suspend. GPIO7 and GPIO44/U0RXD
control EN1/EN2; UART0 console must be disabled on GPIO44. There is no BC1.2 or
Type-C advertised-current detector. Keep VDD_SPI at 3.3 V and never select the
1.8 V memory configuration. Keep backlight PWM low before enabling/removing
its switched input. Use a protected 4.2 V 1S pack with matched temperature
sensing, at least 2 A continuous capability and adequate peak margin. The amp's
speaker wires are both active bridge outputs. Limit output for the actual
speaker (initial sample-peak cap −9 dBFS with the grounded GAIN pin’s 12 dB gain) and verify power/temperature under simultaneous loads.
| Signal | GPIO |
| --- | --- |
| Mic BCLK / WS / DATA | 8 / 41 / 10 |
| Speaker BCLK / WS / DIN / enable | 11 / 12 / 13 / 14 |
| TALK / privacy sense | 6 / 15 |
| LCD MOSI / SCK / CS / DC / reset / PWM | 16 / 17 / 18 / 21 / 47 / 48 |
| Status R / G / B | 4 / 5 / 9 |
| USB D− / D+ | 19 / 20 |
| Battery ADC / measurement enable | 1 / 38 |
| Charge / power-good / haptic | 2 / 39 / 40 |
| Backlight input enable | 42 |
| Charger EN1 / EN2 | 7 / 44 |
| ROM BOOT | 0 |
BOOT/RESET are service switches; no approve/reject buttons or encoder are fitted.
[Chip notes](docs/bare-s3.md) and [LCD pinout](docs/lcd-interface.md) give details.
## Top assembly and connected service
The uploaded assembly PDF is mechanical reference material, not executable
instructions or fabrication approval. Its case is 72 × 53.5 × 16 mm. All devices
are on PCB top, facing the internal battery/rear cover; the front LCD flex folds
to this face. Coordinates are not mirrored. Four Ø1.8 mm mounts are at
(±31.5,±22). Mic datums are (±28,21.5), TALK (0,20.5), privacy (−29.5,3), power
(29.5,−6), USB (0,−19.75) and LCD connector (21.5,3.5).
The revised 3D allocation uses a maximum 52.5 × 35 × 5.7 mm battery at (−1,5),
25 × 9 × 3 mm speaker at (−13,−19.8), and Ø10 × 3.2 mm motor at (25,−18.5).
The side-entry JST PA header has 6.2 mm standard mated height. Verify actual
pack swelling, wire bends, switch linkages, acoustic ducts, USB opening and
LCD flex/latch clearance on an assembled prototype. Off-board candidates are
not a qualified assembled BOM. All supplier model bytes and transformed bounds
are now checked. The case depth proposal increases from 16 to 17 mm; the pack
and transducers rise 0.5 mm to clear actual switch CAD. This leaves 0.68 mm
nominal rear clearance after the drawing's battery swelling allocation.
**MUSE runs on a connected phone/computer/backend.** Intended flow is TALK,
record, authenticated Wi-Fi request, recognized voice/progress/response events,
then display, spoken reply, LEDs and vibration. Endpoint access, authentication,
codecs and protocol behavior remain unverified.
## Public tscircuit package
[AnasSarkiz/muse-voice-remote](https://tscircuit.com/AnasSarkiz/muse-voice-remote)
is the public package. Use `tsci push` for this existing project; `tsci init`
is for a new template. [CLI documentation](https://docs.tscircuit.com/command-line/tsci-push).
```sh
npm run registry:prepare
npm run registry:push
```
Preparation requires checked manufacturing evidence for the package version,
stages complete source/imports/native CAD/manufacturing artifacts, and excludes
historical failed router files. Publishing uses `tsci push --include-dist` and
public visibility. Root `circuit.json` and `dist/index/circuit.json` are identical checked output. Local `dist/circuit.json` is the same build output, but the registry invalidates that temporary cache path on source uploads. Publication receipts in
`docs/` identify the actual uploaded version and cloud build; a prepared folder
alone is not publication proof. Credentials are excluded.
