abse/rp2350-mcu-board

RP2350_POUR_REMOVAL_COMPARISON_2026-09-04.md

# Copper-pour removal comparison

**Current local board:** four physical layers; only GND on inner1 and V1V1 on inner2 have copper pours. Top VBUS and bottom V3V3 pours are removed. No manual PCB paths, traces, vias or pour outlines; no parts, values, placements or electrical constraints changed. Nothing published.

## Tests on the complete board

All trials build the full `index.circuit.tsx` using the same published dependencies. The baseline already had no top VBUS pour and an unresolved VBUS width-path failure.

| Trial | DRC errors | Gerber shorts | Connected required nets | Unique via drills | Decision |
| --- | ---: | ---: | ---: | ---: | --- |
| Baseline: GND + V1V1 + V3V3 pours | 0 | 0 | 58/58 | 123 | Comparison baseline |
| Remove bottom V3V3 only | 0 | 0 | 58/58 | 123 | Keep removal |
| Remove inner2 V1V1 only | 1 | 0 | 58/58 | 132 | Reject; restore V1V1 |
| Final rebuild: GND + V1V1 only | 0 | 0 | 58/58 | 123 | Current source |

The V1V1-removal trial converted its four former plane feeds to ordinary automatic routing, removing the obsolete pour target and fanout hint. It did not leave routes targeting a nonexistent plane. Nevertheless it introduced:

- Via117 to crystal resistor R2.pin1 clearance of **0.04 mm**, below **0.1 mm**.
- C11_V1V1 path length **5.609621 mm**, exceeding **5.5 mm**, with two vias.
- Nine additional unique via drills.

That trial was reverted. No attempt was made to remove the ground pour or reduce the physical layer count. Removing a pour does not remove the layer's signal traces.

## Final verification

- Typecheck and explicit complete-board build/render pass.
- 0 generated DRC errors; 0 all-layer Gerber shorts at 100 pixels/mm.
- 58/58 required nets physically connected; 0 opens, shorted groups or unresolved pads.
- **Two connected pour regions and zero floating/unclassified pour fragments** in the physical-copper audit. The removed bottom pour's two floating fragments are gone.
- All 51 component placements, selected parts, values, source connectivity and specified widths/via/crystal limits are preserved.
- All 28 constrained two-port paths and 18 first-plane-contact checks pass. Crystal signals have zero vias; longest path remains 9.489175 mm under the 10 mm limit.
- 183 PCB traces, 125 via records representing 123 unique drills; no drill-clearance violations.

Final source exactly matches the accepted V3V3-removal source. Final Circuit JSON differs only in supplier-footprint warning records from that trial; all source and copper geometry are identical. Final physical connectivity/island, DRC, 0.3 mm width and Gerber checks were rerun; the other trial checks apply to identical geometry.

## Limitations that remain

The existing **VBUS supply-width failure remains**: no continuous 0.3 mm path between USB/regulator and right-header/RGB branches. This was already present after the user's requested top-pour removal. The independent 0.3 mm check passes 2/3 required nets; the 0.12 mm check passes 36/37, failing VBUS only. This is no added regression from removing V3V3, not a claim that every electrical/manufacturing requirement passes.

There are still 56 generated warnings, 11 separately reported net-wide width warnings and the same three full stored-fanout length warnings. First physical plane contact passes those fanout limits, but native warnings are retained. The GPIO header BOM mismatch, pour-neck/spoke current capacity, signal/return-path integrity and manufacturer DFM remain unresolved. **Not order-ready.**

The general floating-island solver repro is prepared locally with its original full-board fixture, but public upload is pending explicit approval. No production copper-pour solver fix or PR has been published.

## Files

- [Live local board](http://localhost:3021/#file=index.circuit.tsx&main_component=index.circuit.tsx)
- [Final PCB snapshot](dist/index/pcb.png)
- [Final circuit JSON](dist/index/circuit.json)
- [Evidence and checkpoints](/Users/abdolsalamallawlabi/Documents/Codex/2026-08-27/work-on-the-complete-rp2350-mcu-2/board-four-layer-20260904/STATUS.md)
- [Prepared solver reproduction](/Users/abdolsalamallawlabi/Documents/Codex/2026-08-27/work-on-the-complete-rp2350-mcu-2/copper-pour-island-repro/tests/repro07-rp2350-floating-islands/README.md)

SHA-256:

```text
index.circuit.tsx: 29363501a3d23be5621898a41c927b408aa4f0337528fc10217a421786c90e33
RP2350A_Essential_KiCad_Reference.circuit.tsx: b8a8160823786226d777cb368892ba005b593e4db916850ae380b8810f42684d
dist/index/circuit.json: b2c017b06ee2ac146a7cf8ba13e4a6654aea8f4fccdbfbfb3482c3fea3956cf6
dist/index/pcb.png: 0add49f0e6adbc8a429bf40283b5f77a89235e6ccfcb715b629d73fa8585d565
```