abse/rp2350-mcu-board

RP2350_COPPER_POUR_UPDATE_2026-09-04.md

# Local copper-pour updates

**Historical checkpoints below.** The bottom 3.3 V pour has now also been removed after regression testing. See [the current pour-removal comparison](RP2350_POUR_REMOVAL_COMPARISON_2026-09-04.md) for current results and hashes.

## Current: top VBUS pour removed

The user subsequently requested complete removal of the top VCC/VBUS pour. `VBUS_POUR_TOP` has been removed from `index.circuit.tsx`; **there are now no top-layer pours**. GND on inner1, V1V1 on inner2 and V3V3 on bottom remain unchanged. No manual PCB paths, traces or vias were introduced, and nothing was published.

Fresh complete-board verification:

| Check | No-top-pour result |
| --- | --- |
| Typecheck and complete-board build/render | Pass |
| Generated DRC errors | 0 |
| All-layer Gerber shorts, 100 pixels/mm | 0 |
| Physically connected required nets | 58/58 |
| Opens / shorted groups / unresolved pads | 0 / 0 / 0 |
| Required 0.3 mm supply-path checks | **2/3 pass; VBUS fails** |
| Crystal signal vias | 0 |
| Longest crystal signal path | 9.489175 mm |

The VBUS net is physically connected, but it lacks a continuous 0.3 mm copper path between the USB/regulator branch and the right-header/RGB branch. Excluding undersized routes separates those groups. This limitation is reported rather than silently restoring the pour. No further rerouting was requested or performed beyond the automatic rebuild.

All 51 placements, parts, values, source connectivity and specified constraints are preserved. All 28 constrained two-port paths and 18 first-plane-contact checks pass. The same 56 generated warnings, 11 separate width warnings, three native full stored-fanout length warnings, and GPIO header BOM mismatch remain. The two bottom 3.3 V floating fragments also remain. **Not order-ready.**

The solver repro is prepared locally but not pushed; public upload of the full unpublished four-layer fixture and snapshots still requires explicit approval. See the local repro and evidence links below. The live server remains [localhost:3021](http://localhost:3021/#file=index.circuit.tsx&main_component=index.circuit.tsx).

Current SHA-256 values:

```text
index.circuit.tsx: 387c76d0a580f02ccb29c315b7f42cc40dfececbd13ec43fd6615251a5153a41
dist/index/circuit.json: de11e084c06695cf42e2ec926767f740f7298b4817dea3db0765e27291e51683
dist/index/pcb.png: 3fc6a9363fb1f486e3893108643864175eb959fad931a490a489e7bac813f002
```

## Historical: bounded VBUS pour trial

The following describes the preceding trial, before the user requested removal. It is not the current source.

The complete four-layer `index.circuit.tsx` board now uses a bounded top VBUS pour on the right-hand power side, not whole-board top fill. **Local only; not an assembly release.** This supersedes the earlier four-layer report's copper-pour counts and source/output hashes.

## Is the top pour used?

Yes. It is **VBUS (USB 5 V), not 3.3 V or ground**. The connected copper joins the USB/regulator supply network to the right-header/RGB supply network. An overly restricted trial retained basic connectivity but failed the required 0.3 mm path check, so it was rejected. The accepted area extends below the existing routing barrier and preserves the required supply connection.

The source defines a simple rectangular pour envelope, x 10.5 to 23.7 mm and y -31.7 to 28 mm. Clearances and final copper contours are generated by the published pour solver. This change does introduce a bounded **pour outline**, as requested; it does not introduce `pcbPath`, manual PCB traces, manually placed vias, route caches, dependency overrides, patches or routing-algorithm changes.

## Before and after

| Check | Whole-board top pour | Bounded top pour |
| --- | ---: | ---: |
| Top VBUS BREP regions | 82 | 1 |
| Physically connected top regions | 3 | 1 |
| Floating top fragments | 73 | 0 |
| Too small to classify at 100 px/mm | 6 | 0 |
| Top pour copper area | 2255.912 mm² | 611.359 mm² |
| Generated DRC errors | 0 | 0 |
| All-layer Gerber shorts | 0 | 0 |
| Physically connected required nets | 58/58 | 58/58 |

Top pour copper area is reduced by 72.9%. U1's center square remains its grounded exposed pad. There is no top VBUS fill under/around U1 in the new design.

Typecheck and explicit complete-board build/render pass. Physical connectivity at 100 pixels/mm finds no opens, shorted net groups or unresolved pads. Supplemental required-width checks pass for 37/37 nets at 0.12 mm and 3/3 at 0.3 mm. All 28 constrained two-port paths and 18 first-plane-contact checks pass. Crystal signals remain via-free; longest path is 9.489175 mm under the 10 mm limit. The drill audit finds zero clearance violations among 123 unique via drills. All 51 component placements, values, selected parts, source connectivity and specified constraints are preserved.

The RP2350 essentials still live in a reusable JSX component, but it returns ordinary placement groups. It is not an independently routed MCU subcircuit; the complete board routes together.

## Remaining issues

- Bottom 3.3 V copper still contains two floating fragments. Inner1 GND and inner2 V1V1 each have one connected pour region.
- The general orphan-removal issue is reproduced in the copper-pour-solver repository; no production solver fix was made. The repro includes a minimal expected-failing test and full-board/U1 snapshots. Public PR creation awaits approval to expose the unpublished four-layer fixture.
- The same 56 generated warnings remain, including three full stored-route-length warnings. First actual plane contact meets those limits, but the native warnings were not removed or suppressed. A separate published width checker reports 11 mixed-width net warnings.
- Pour-neck/spoke current capacity and manufacturer DFM are not certified by these finite-resolution checks. The GPIO header BOM mismatch remains unresolved. Do not order assembly from the current BOM.

## View and evidence

- [Live local board](http://localhost:3021/#file=index.circuit.tsx&main_component=index.circuit.tsx)
- [PCB snapshot](dist/index/pcb.png)
- [PCB SVG](dist/index/pcb.svg)
- [Current circuit JSON](dist/index/circuit.json)
- [Verification evidence and current status](/Users/abdolsalamallawlabi/Documents/Codex/2026-08-27/work-on-the-complete-rp2350-mcu-2/board-four-layer-20260904/STATUS.md)
- [Local solver reproduction](/Users/abdolsalamallawlabi/Documents/Codex/2026-08-27/work-on-the-complete-rp2350-mcu-2/copper-pour-island-repro/tests/repro07-rp2350-floating-islands/README.md)

Published project version 0.0.7 remains the six-layer checkpoint. No board publication occurred during this update.

SHA-256:

```text
index.circuit.tsx: 0affe6ed8fbb55fc7ff4dd68ca16d83e7a3bf9f6bde7e89b836f6207faa495e1
RP2350A_Essential_KiCad_Reference.circuit.tsx: b8a8160823786226d777cb368892ba005b593e4db916850ae380b8810f42684d
dist/index/circuit.json: 4d031fb3edc4db9396fa8330c0c5a8c6d04cb7e3d3d634e3c3b3e3ecfd672285
dist/index/pcb.png: 0c47fadffaf6a1a2b6abb28a9784127193766c9243cc3237403dbab2ed249060
```