README.md
# MSPM0G3507 USB-C development board
This is a JLCPCB-oriented, two-layer development board built around TI's 80 MHz Arm Cortex-M0+ MSPM0G3507. Its outline is a uniform 90 mm Ć 21 mm rectangle: the same width as a Raspberry Pi Pico, with only the additional length needed for the USB-UART bridge, accessory connectors, RGB LED, controls, and four mounting holes. A CH340C USB-to-UART bridge makes the factory ROM bootloader accessible from the USB-C connector. The PCB is routed entirely by tscircuit's default autorouter; the source contains no manual PCB traces, vias, or route hints. Autorouted through-vias use 0.30 mm drills and 0.45 mm copper pads.
The two 1Ć20 rows use the Raspberry Pi Pico's breadboard-friendly 17.78 mm (0.7 inch) row spacing on a 2.54 mm grid. Their centers remain at y = Ā±8.89 mm, so the headers align with a breadboard exactly as before. The immediately adjacent outer breadboard-hole centers sit 0.93 mm beyond the PCB edge. As with the Pico geometry, a nominal 2.54 mm square jumper housing overlaps the PCB outline by about 0.34 mm in plan view, although the hole centers remain outside the board. The supplier-matched header footprint uses 1.6 mm round lands and 1.05 mm drills, leaving a 0.275 mm annular ring and 0.81 mm copper-to-edge clearance. It is not electrically or binary compatible with an RP2040/Pico.
## Features
- MSPM0G3507SPTR: 80 MHz Cortex-M0+, 128 KB flash, 32 KB SRAM, CAN-FD, ADC, DAC, op amps, UART, SPI, and I2C.
- Reversible USB-C data connection through USBLC6-2SC6 ESD protection to a 3.3 V CH340C USB-UART bridge.
- AP2112K 3.3 V regulator with explicit `VBUS_5V`, `VDD_3V3`, and `GND` nets and labelled header pins.
- BOOT and RESET buttons for the factory UART ROM bootloader, plus exposed SWDIO and SWCLK.
- Active-high common-cathode RGB user/debug LED on PB2/PB3/PB14 and a separate green 3.3 V power LED.
- JST-SH I2C connector, JST-SH SPI display connector, and Seeed Grove-compatible I2C connector, all using 3.3 V logic.
- Two breadboard-spaced, bottom-silkscreen-labelled 1Ć20 GPIO headers; four isolated 2.7 mm mounting holes for M2.5 hardware; and three separate SMT fiducials.
- An ANSI-B schematic sheet divided into eight labelled functional sections for the USB-C receptacle, USB protection/UART bridge, power, MCU controls, RGB LED, I2C, SPI, and headers.
- Every placed component has an explicit manufacturer part number, JLCPCB/LCSC part number, verified pin/pad mapping, supplier-matched footprint, and courtyard.
- No external crystals: both the MSPM0G3507 and CH340C use internal clocks in this design.
## USB programming
The USB-C connector appears on the host as a CH340 serial port. This is not RP2040 UF2 drag-and-drop programming.
For a blank MCU, connect USB-C and use TI's MSPM0 BSL host software with the CH340 serial port. To force the ROM bootloader later:
1. Hold **BOOT**.
2. Press and release **RESET**.
3. Release **BOOT** after reset.
4. Program a TI-TXT or supported image with TI's MSPM0 BSL host/GUI over the CH340 serial port.
The bridge is wired CH340 TXD ā 1 kĪ© ā PA11/BSL_RX and PA10/BSL_TX ā 1 kĪ© ā CH340 RXD. PA18 is held low normally and the BOOT button drives it to 3.3 V for BSL invocation. SWDIO, SWCLK, RESET, 3V3, and GND are also exposed for an external debug probe.
## Connector pinouts
The same pin numbers and signal names are printed on the PCB silkscreen.
| Connector | Pinout |
|---|---|
| JST-SH I2C | 1 GND, 2 3V3, 3 SDA/PA0, 4 SCL/PA1 |
| Grove I2C | 1 SCL/PA1, 2 SDA/PA0, 3 3V3, 4 GND |
| JST-SH SPI | 1 GND, 2 3V3, 3 SCK/PB9, 4 MOSI/PB8, 5 MISO/PB7, 6 CS/PB6, 7 DC/PA8, 8 RESET/PA9 |
The I2C bus has 4.7 kĪ© pull-ups to `VDD_3V3`. Do not apply 5 V to any GPIO or accessory signal. Do not drive the 3V3 rail from another supply while USB is connected unless the supplies are safely isolated.
## Fabrication files
The synchronized release files are in [`outputs/`](outputs/):
- `MSPM0G3507_USB_C_JLCPCB_Gerbers.zip`
- `MSPM0G3507_USB_C_JLCPCB_BOM.csv`
- `MSPM0G3507_USB_C_JLCPCB_CPL.csv`
- `MSPM0G3507_USB_C_PCB.svg`
- `MSPM0G3507_USB_C_Schematic.svg`
- `MSPM0G3507_USB_C_Assembly.svg`
Upload the Gerber ZIP for PCB fabrication and the standalone BOM/CPL for PCBA. All SMT placements are on the top side. The two 1Ć20 headers and the Grove connector are through-hole parts; select a JLCPCB assembly service that supports those parts or omit them from assembly and hand-solder them.
After `npm run build`, run `npm run release:artifacts` to regenerate the PCB, schematic, assembly SVGs, Gerbers, BOM, and CPL from the same built Circuit JSON. The release command also replaces the exporter's generic embedded assembly tables with the exact manufacturer-rich JLCPCB BOM/CPL and prevents stale or internally inconsistent order files.
## Verification
The release audit verifies typechecking, tscircuit netlist/pin/placement/routing checks, `tsci check shorts`, the uniform 90 mm Ć 21 mm Pico-width outline, 17.78 mm header-row spacing, 2.54 mm header pitch, adjacent breadboard-hole-center exposure, header-pad edge clearance, isolated mounting-hole coordinates, the schematic sheet and all eight section labels, complete courtyards, exact BOM identifiers, switch semantics and nets, LED polarity, USB-C A/B contacts, USB-UART wiring, top-only stencil data, through-via drill coverage, and synchronized Gerber/BOM/CPL files. `npm run check:schematic-placement` additionally fails on schematic symbol, spacing, or label-collision issues while reporting trace-simplification suggestions as non-blocking advisories.
The protected D+/Dā pair is routed together on the top layer with no vias and zero measured skew. All connector-to-ESD USB data paths are top-layer and via-free; worst measured end-to-end skew is below 0.8 mm. The MCU VCORE bypass route is top-layer, via-free, and below 2 mm. USB-C shield slots are checked in the actual Excellon output for the correct orientation.
The RGB channels are red on PB2, green on PB3, and blue on PB14. Each anode has its own 330 Ī© resistor; writing a channel high turns it on, and PWM can mix colors or adjust brightness. The LED uses otherwise-unexposed MCU pins, so all header GPIO assignments remain unchanged.
All 25 unique JLCPCB part numbers in the 38-placement BOM had exact manufacturer-part-number matches and positive live inventory at the final 2026-09-06 audit. Inventory changes, so run `npm run check:jlc-stock` immediately before ordering.
As with any new hardware design, manufacture a small first-article batch and validate power, USB enumeration, bootloader entry, programming, and I/O before committing to production volume.
