AnasSarkiz/magnetic-shutter-remote-r8

evidence/R9-routing-2026-10-13/FINAL-REVIEW.md

# R9 bare ESP32-C3 prototype review — 2026-10-14

**Routing and local fabrication/CAD checks pass. Ordering remains blocked by unconfirmed supplier filled/capped-via processing and cost.** Physical qualification follows prototype assembly.

U1 is the bare **ESP32-C3FH4 / C2858491**, not a module. The PCB is **44 × 56 × 1 mm**, two layers. Power uses top/bottom copper. The RGB-ring idea remains excluded.

| Final check | Actual result |
| --- | --- |
| Native routing | 177 traces; 0 generated errors, shorts, dangling connections or hole/trace errors |
| Physical copper continuity | All 38 terminal nets connected; no antenna/shutter intrusions |
| Declared clearances | 0 failures at 0.15 mm copper, 0.35 mm via/SMT and 0.50 mm distinct via drill-edge spacing |
| Trace widths and power | All 177 tracks meet assigned widths; chip voltage budget 3.087917 V, regulator input 2.920818 V |
| RF/clock geometry | Continuous required bottom reference; no signal vias or prohibited antenna copper |
| Native fabrication exports | All 12 Gerber/Excellon files independently parsed; copper, drills, mask, paste and outline match source |
| Stencil/mask/silk | 210 apertures; 0 process failures; minimum area ratio 0.699999, minimum mask web 0.118262 mm |
| BOM/CPL | 63 fitted references, 33 exact supplier identities; all placement rotations resolved |
| Supplier documents/stock | 24 manufacturer PDFs cover 33 identities, hashes verified; public stock passed 2026-10-14 for five boards, not reserved |
| Actual enclosure fit | All 63 supplier models, board, maximum battery, four mounts and side shutter pass nominal CAD checks |
| Actual native assembly readback | 38 closed/exploded model-position and electronics triangle-count checks pass |
| Print files | Eight enclosure STL files regenerated and independently checked |
| Regressions | 12 product/schematic/storage tests, 858 assertions; 49 CAM tests; all pass |
| Hosted setup/smoke | `bash cloud/setup.sh` and `bash cloud/smoke.sh` pass; formatting/typecheck, 38 Python tests and 2 power-metadata tests pass |
| Frozen baseline | 129/129 recorded hashes pass |

Read [DATASHEET-REVIEW.md](DATASHEET-REVIEW.md) for the actual pin, supply, boot/reset, UART, clock/RF, charger, regulator, current and protected-cell decisions. Component estimate is approximately **US$8.15 per board**, excluding assembly, attrition, shipping, battery, enclosure and filled/capped-via processing; this is not a quotation.

Four U1 exposed-pad GND vias intentionally use **0.30 mm drill / 0.45 mm pad through both layers**. They require **epoxy filling plus plated copper caps** with a planar solderable finish. Tenting or soldermask plugging is not equivalent. All other via-in-pad is rejected; there are no blind/buried vias. Supplier processed-preview and quotation flags remain false in `fabrication/r9-process.json`. No supplier upload or contact was performed.

The USB library footprint had a real CAM failure: its 0.8 mm-wide slots were too short for the selected fabrication rule. The retained HRO drawing specifies 0.6 × 1.4 / 1.7 mm slots. `src/r9-usb-footprint.tsx` explicitly authors those dimensions and adequate annuli, preserving terminal centers/identifiers and SMT copper. Original supplier imports remain unchanged. One paste polygon is aligned to its exact copper polygon. [USB-SLOT-REVIEW.md](USB-SLOT-REVIEW.md) records the drawing and correction; no generated Circuit JSON or Gerber was edited.

The stencil checker incorrectly assumed equal paste/land centroids. Actual asymmetric L2/L4 apertures differ by 0.031063 mm. Attribution now requires unique actual fitted-land contact, correct component/layer and containment inside exported mask openings. Negative tests reject disconnected apertures, off-mask paste and bridges to another component. No process minima or geometry comparison tolerances were relaxed. The former R8 antenna regression remains on its retained R8 fixture, with an additional equivalent R9 antenna test.

The enclosure remains **90 × 78 × 34 mm**, with the actual PCB and protected **ASR00012 / Hondark 803040PL** maximum **32 × 43 × 8.5 mm** cell. Nominal checks include 151 closure samples and four shutter positions. The cap-to-switch gap is 0.149972 mm; the 0.35 mm stop allows the switch's maximum 0.20 mm travel. Actual friction, return, tolerance stack and stop strength remain untested. Cell insulation/swelling/strain relief, the **U5-to-cell thermal bridge**, USB plug/service harness and fasteners need physical qualification. U5 is near the cell, not touching it. RF/matching/harmonics, crystal drive/frequency, BLE/iPhone operation and MagSafe/phone/case clearance also need prototype tests.

The model retains all supplier geometry: eight bounded, losslessly indexed GLBs contain 62 parts plus PCB; L3 uses its exact supplier OBJ; ten mechanical models complete the assembly. No decimation or surrogate board is used. Independent triangle/attribute/image/material proofs pass. The official writer's separate attribute layout avoids a reproduced byteStride defect in the pinned native GLB reader; see local issue116. Current renders are [closed](../../product/closed.png), [exploded](../../product/exploded.png) and [phone-facing](../../product/phone-facing.png). The standard downloadable viewer is `dist/enclosure/viewer.html` with 19 embedded model assets.

Four A4 schematic pages keep every component explanation on the component's page. Actual final CLI style analysis retains two L2 tool findings: false crystal classification and ignored custom-symbol rotation (issue106). Native checks separately retain J3 orientation metadata warning (issue004), two U1 padding warnings and passive/MOSFET pin-metadata warnings. Original 075/076/004/084 and the separate missing `3V3` importer metadata issue remain explicit. These warnings are not hidden or counted as physical copper shorts.

**Hosted browser/UI verification did not pass.** A minimal browser health page returned `ERR_BLOCKED_BY_ADMINISTRATOR` on a `data:` URL. Earlier analyzer attempts timed out before any analyzer-host request. This establishes a hosted browser-policy restriction, not a demonstrated tscircuit defect or blocked external hostname. No browser-policy/proxy bypass was attempted. Actual native GLB readback and renders pass.

Programming uses standard JST programmer 0.8.0 J5 → board J3: 1 RX(GPIO20) ← programmer TX, 2 GND, 3 TX(GPIO21) → programmer RX. Signals are 3.3 V; this port supplies no target power, BOOT or EN. Battery ON, USB unplugged; hold BOOT while pulsing RESET. Actual cable mating/polarity and hardware flashing remain untested.

Observed runtime: **32 GiB cgroup limit**, CPU quota 4 / affinity 5, Node 25.6.0, Bun 1.3.9, Python 3.12.14; CAM Python 3.14.7. Memory is observed, not a guaranteed plan allocation; no guaranteed task runtime limit is advertised. Heavy jobs used the unchanged serial `python3 cloud/run-heavy.py` guard; all OOM counters remain zero. Setup/start stays lightweight and preserves this and later authorized task branches. No access/auth/network scope was broadened and no secrets were added.

Branch: `board/r9-bare-esp32c3-20261013`. HEAD: `208aa007ee98d432b6ba510776af323822f832db`. Final Circuit JSON SHA256: `55c3bce87456eb5e58ce1bf232dc6f93ed96205ea12e7dfc874c0fb64763ad5e`. Changes remain **uncommitted and unpublished**. No main/frozen baseline/firmware/light setup/start/memory-guard changes, SDK builds, commits, pushes, publication, assembler uploads, orders, payment or supplier contact occurred in this continuation. This does not prohibit later user-authorized engineering/publication after required gates. Frozen baselines remain immutable; ordering/payment/contact require separate authorization.

[Fabrication package instructions](../../fabrication/R9/README.md) identify the exact Gerber ZIP, BOM and CPL. `checks-and-artifacts.json` binds current reports/artifacts to hashes. `logs/` retains actual successes and failures, including the initial typecheck failure and corrected smoke pass; no first-attempt success is fabricated. Exact final Git paths/status and full diff are retained in `/workspace/r9-routing-review-20261013/final-git-status.txt` and `final-git.diff`.