0hmX/pcbgolf-modular-checkpoint
A partial 3D assembly of seven separate PCBs—five USB carriers, an MCU board, and an SBU board—with modeled USB/DC connectors, but no routing, wiring, supports, or tilted-board mounting.
- Version
- 0.0.6
- License
- UNLICENSED
- Stars
- 0
preview-parity.json
PCB
Schematic
{
"scope": "all native reference/value/pad/net identities, copper layers and via counts; not geometric equivalence",
"boards": [
{
"id": "core19",
"native_footprints": 20,
"native_pad_nodes": 180,
"preview_source_ports": 180,
"native_vias": 22,
"layers": 2,
"preview_board_mm": [
18,
10,
0.4
],
"omitted_blank_non_electrical_anchor_pads": [
"U17",
"U17",
"U17",
"U17",
"U3",
"U3",
"U3",
"U3",
"U3",
"U3",
"U3",
"U3",
"U3",
"U3",
"U3",
"U3",
"U3",
"U3",
"U3",
"U3",
"R127",
"R127"
],
"net_label_restorations": [],
"pour_net_links": [
{
"pour": "pcb_copper_pour_0",
"native_net": "GND"
},
{
"pour": "pcb_copper_pour_1",
"native_net": "GND"
},
{
"pour": "pcb_copper_pour_2",
"native_net": "GND"
},
{
"pour": "pcb_copper_pour_3",
"native_net": "GND"
},
{
"pour": "pcb_copper_pour_4",
"native_net": "GND"
},
{
"pour": "pcb_copper_pour_5",
"native_net": "GND"
},
{
"pour": "pcb_copper_pour_6",
"native_net": "GND"
},
{
"pour": "pcb_copper_pour_7",
"native_net": "GND"
},
{
"pour": "pcb_copper_pour_8",
"native_net": "GND"
},
{
"pour": "pcb_copper_pour_9",
"native_net": "GND"
}
],
"errors": [],
"pass": true
},
{
"id": "CH1_SBU1",
"native_footprints": 16,
"native_pad_nodes": 31,
"preview_source_ports": 31,
"native_vias": 0,
"layers": 2,
"preview_board_mm": [
7.6,
6.4,
0.4
],
"omitted_blank_non_electrical_anchor_pads": [
"R78",
"R78",
"R98",
"R98"
],
"net_label_restorations": [],
"pour_net_links": [],
"errors": [],
"pass": true
},
{
"id": "CH2_SBU1",
"native_footprints": 16,
"native_pad_nodes": 31,
"preview_source_ports": 31,
"native_vias": 0,
"layers": 2,
"preview_board_mm": [
7.6,
6.4,
0.4
],
"omitted_blank_non_electrical_anchor_pads": [
"R79",
"R79",
"R99",
"R99"
],
"net_label_restorations": [],
"pour_net_links": [],
"errors": [],
"pass": true
},
{
"id": "CH3_SBU1",
"native_footprints": 16,
"native_pad_nodes": 31,
"preview_source_ports": 31,
"native_vias": 0,
"layers": 2,
"preview_board_mm": [
7.6,
6.4,
0.4
],
"omitted_blank_non_electrical_anchor_pads": [
"R80",
"R80",
"R100",
"R100"
],
"net_label_restorations": [],
"pour_net_links": [],
"errors": [],
"pass": true
},
{
"id": "CH4_SBU1",
"native_footprints": 16,
"native_pad_nodes": 31,
"preview_source_ports": 31,
"native_vias": 0,
"layers": 2,
"preview_board_mm": [
7.6,
6.4,
0.4
],
"omitted_blank_non_electrical_anchor_pads": [
"R81",
"R81",
"R101",
"R101"
],
"net_label_restorations": [],
"pour_net_links": [],
"errors": [],
"pass": true
},
{
"id": "CH1_SBU2",
"native_footprints": 16,
"native_pad_nodes": 31,
"preview_source_ports": 31,
"native_vias": 0,
"layers": 2,
"preview_board_mm": [
7.6,
6.4,
0.4
],
"omitted_blank_non_electrical_anchor_pads": [
"R102",
"R102",
"R122",
"R122"
],
"net_label_restorations": [],
"pour_net_links": [],
"errors": [],
"pass": true
},
{
"id": "CH2_SBU2",
"native_footprints": 16,
"native_pad_nodes": 31,
"preview_source_ports": 31,
"native_vias": 0,
"layers": 2,
"preview_board_mm": [
7.6,
6.4,
0.4
],
"omitted_blank_non_electrical_anchor_pads": [
"R103",
"R103",
"R123",
"R123"
],
"net_label_restorations": [],
"pour_net_links": [],
"errors": [],
"pass": true
},
{
"id": "CH3_SBU2",
"native_footprints": 16,
"native_pad_nodes": 31,
"preview_source_ports": 31,
"native_vias": 0,
"layers": 2,
"preview_board_mm": [
7.6,
6.4,
0.4
],
"omitted_blank_non_electrical_anchor_pads": [
"R104",
"R104",
"R124",
"R124"
],
"net_label_restorations": [],
"pour_net_links": [],
"errors": [],
"pass": true
},
{
"id": "CH4_SBU2",
"native_footprints": 16,
"native_pad_nodes": 31,
"preview_source_ports": 31,
"native_vias": 0,
"layers": 2,
"preview_board_mm": [
7.6,
6.4,
0.4
],
"omitted_blank_non_electrical_anchor_pads": [
"R105",
"R105",
"R125",
"R125"
],
"net_label_restorations": [],
"pour_net_links": [],
"errors": [],
"pass": true
},
{
"id": "st7p70_mcu",
"native_footprints": 9,
"native_pad_nodes": 66,
"preview_source_ports": 66,
"native_vias": 7,
"layers": 2,
"preview_board_mm": [
7.7,
7.7,
0.4
],
"omitted_blank_non_electrical_anchor_pads": [
"U3",
"U3",
"U3",
"U3",
"U3",
"U3",
"U3",
"U3",
"U3",
"U3",
"U3",
"U3",
"U3",
"U3",
"U3",
"U3"
],
"net_label_restorations": [
[
"P3V3",
"+3V3"
],
[
"P3V3",
"+3V3"
],
[
"unconnected_U3_PC15_OSC32_OUT_Pad4",
"unconnected-(U3-PC15-OSC32_OUT-Pad4)"
],
[
"unconnected_U3_PC15_OSC32_OUT_Pad4",
"unconnected-(U3-PC15-OSC32_OUT-Pad4)"
],
[
"Net_U3_PH0",
"Net-(U3-PH0)"
],
[
"Net_U3_PH0",
"Net-(U3-PH0)"
],
[
"Net_U3_PH1",
"Net-(U3-PH1)"
],
[
"Net_U3_PH1",
"Net-(U3-PH1)"
],
[
"Net_U3_PF7",
"Net-(U3-PF7)"
],
[
"Net_U3_PF7",
"Net-(U3-PF7)"
],
[
"Net_U3_PF8",
"Net-(U3-PF8)"
],
[
"Net_U3_PF8",
"Net-(U3-PF8)"
],
[
"Net_U3_PF9",
"Net-(U3-PF9)"
],
[
"Net_U3_PF9",
"Net-(U3-PF9)"
],
[
"Net_U3_PF10",
"Net-(U3-PF10)"
],
[
"Net_U3_PF10",
"Net-(U3-PF10)"
],
[
"Net_U3_PC0",
"Net-(U3-PC0)"
],
[
"Net_U3_PC0",
"Net-(U3-PC0)"
],
[
"Net_U3_PC1",
"Net-(U3-PC1)"
],
[
"Net_U3_PC1",
"Net-(U3-PC1)"
],
[
"Net_U3_PC2_C",
"Net-(U3-PC2_C)"
],
[
"Net_U3_PC2_C",
"Net-(U3-PC2_C)"
],
[
"Net_U3_PC3_C",
"Net-(U3-PC3_C)"
],
[
"Net_U3_PC3_C",
"Net-(U3-PC3_C)"
],
[
"unconnected_U3_PB3_Pad41",
"unconnected-(U3-PB3-Pad41)"
],
[
"unconnected_U3_PB3_Pad41",
"unconnected-(U3-PB3-Pad41)"
],
[
"unconnected_U3_PB4_Pad42",
"unconnected-(U3-PB4-Pad42)"
],
[
"unconnected_U3_PB4_Pad42",
"unconnected-(U3-PB4-Pad42)"
]
],
"pour_net_links": [
{
"pour": "pcb_copper_pour_0",
"native_net": "GND"
},
{
"pour": "pcb_copper_pour_1",
"native_net": "GND"
},
{
"pour": "pcb_copper_pour_2",
"native_net": "GND"
}
],
"errors": [],
"pass": true
}
],
"pass": true
}