0hmX/am3352-ddr-track-a-local-dfm-wip-20261007
Experimental RJ45-corrected board with isolated PG indication. 1005/1005 source joins pass; 15 expanded-guard physical errors, sourcing and qualification gates remain. Not fabrication-ready.
- Version
- 0.0.14
- License
- unset
- Stars
- 0
scripts/usb-c-ports.route.json
{
"bbox": [
-28,
30,
3,
26.5
],
"res": 0.05,
"clearance": 0.12,
"viaClearance": 0.13,
"viaCost": 60,
"layers": [
"top",
"inner2",
"inner4",
"bottom"
],
"previousOutput": "layout/UsbCPortRoutes.tsx",
"routes": [
{
"name": "USBCP_CC1",
"net": "USBC_CC1",
"width": 0.12,
"from": [
"J_POWER",
"A5"
],
"fromSel": ".Power_input > .J_POWER > .A5",
"to": [
"U_PD",
"15"
],
"toSel": ".Power_input > .U_PD > .15",
"layers": [
"top",
"inner2",
"inner4",
"bottom"
],
"viaCost": 60
},
{
"name": "USBCP_CC2",
"net": "USBC_CC2",
"width": 0.12,
"from": [
"J_POWER",
"B5"
],
"fromSel": ".Power_input > .J_POWER > .B5",
"to": [
"U_PD",
"14"
],
"toSel": ".Power_input > .U_PD > .14",
"layers": [
"top",
"inner2",
"inner4",
"bottom"
],
"viaCost": 60
},
{
"name": "USBCP_PD_VBUS_CAP",
"net": "USBC_VBUS_RAW",
"width": 0.2,
"from": [
"U_PD",
"18"
],
"fromSel": ".Power_input > .U_PD > .18",
"to": [
"C_PD_VBUS",
"pin2"
],
"toSel": ".Power_input > .C_PD_VBUS > .pin2",
"layers": [
"top",
"inner2",
"inner4",
"bottom"
],
"viaCost": 60
},
{
"name": "USBCP_PD_VBUS_FEED",
"net": "USBC_VBUS_RAW",
"width": 0.2,
"from": [
"C_PD_VBUS",
"pin2"
],
"fromSel": ".Power_input > .C_PD_VBUS > .pin2",
"to": [
"C_RAW_EFUSE",
"pin1"
],
"toSel": ".Power_input > .C_RAW_EFUSE > .pin1",
"layers": [
"top",
"inner2",
"inner4",
"bottom"
],
"viaCost": 60
},
{
"name": "USBCP_NOR_VCC",
"net": "USBC_VBUS_RAW",
"width": 0.2,
"from": [
"U_TYPEC_NOR",
"5"
],
"fromSel": ".Power_input > .U_TYPEC_NOR > .5",
"to": [
"C_RAW_NOR",
"pin1"
],
"toSel": ".Power_input > .C_RAW_NOR > .pin1",
"layers": [
"top",
"inner2",
"inner4",
"bottom"
],
"viaCost": 60
},
{
"name": "USBCP_CONTRACT_N",
"net": "PD_CONTRACT_N",
"width": 0.12,
"from": [
"U_PD",
"3"
],
"fromSel": ".Power_input > .U_PD > .3",
"to": [
"U_TYPEC_NOR",
"3"
],
"toSel": ".Power_input > .U_TYPEC_NOR > .3",
"layers": [
"top",
"inner2",
"inner4",
"bottom"
],
"viaCost": 60
},
{
"name": "USBCP_VDC_OUT",
"net": "SYS_5V",
"width": 0.15,
"from": [
"U_PD",
"11"
],
"fromSel": ".Power_input > .U_PD > .11",
"to": [
"U_INPUT_EFUSE",
"5"
],
"toSel": ".Power_input > .U_INPUT_EFUSE > .5",
"layers": [
"top",
"inner2",
"inner4",
"bottom"
],
"viaCost": 60
},
{
"name": "USBCP_ISNK_A",
"net": "PD_ISNK_COARSE",
"width": 0.12,
"from": [
"U_PD",
"5"
],
"fromSel": ".Power_input > .U_PD > .5",
"to": [
"R_PD_ISNK_UP",
"pin2"
],
"toSel": ".Power_input > .R_PD_ISNK_UP > .pin2",
"layers": [
"top",
"inner2",
"inner4",
"bottom"
],
"viaCost": 60
},
{
"name": "USBCP_ISNK_B",
"net": "PD_ISNK_COARSE",
"width": 0.12,
"from": [
"R_PD_ISNK_UP",
"pin2"
],
"fromSel": ".Power_input > .R_PD_ISNK_UP > .pin2",
"to": [
"R_PD_ISNK_DN",
"pin2"
],
"toSel": ".Power_input > .R_PD_ISNK_DN > .pin2",
"layers": [
"top",
"inner2",
"inner4",
"bottom"
],
"viaCost": 60
},
{
"name": "USBCP_VDDD_A",
"net": "PD_VDDD",
"width": 0.2,
"from": [
"U_PD",
"23"
],
"fromSel": ".Power_input > .U_PD > .23",
"to": [
"C_PD_VDDD",
"pin2"
],
"toSel": ".Power_input > .C_PD_VDDD > .pin2",
"layers": [
"top",
"inner2",
"inner4",
"bottom"
],
"viaCost": 60
},
{
"name": "USBCP_VDDD_B",
"net": "PD_VDDD",
"width": 0.2,
"from": [
"C_PD_VDDD",
"pin2"
],
"fromSel": ".Power_input > .C_PD_VDDD > .pin2",
"to": [
"C_PD_VDDD_HF1",
"pin2"
],
"toSel": ".Power_input > .C_PD_VDDD_HF1 > .pin2",
"layers": [
"top",
"inner2",
"inner4",
"bottom"
],
"viaCost": 60
},
{
"name": "USBCP_VDDD_C",
"net": "PD_VDDD",
"width": 0.2,
"from": [
"C_PD_VDDD_HF1",
"pin2"
],
"fromSel": ".Power_input > .C_PD_VDDD_HF1 > .pin2",
"to": [
"C_PD_VDDD_HF2",
"pin2"
],
"toSel": ".Power_input > .C_PD_VDDD_HF2 > .pin2",
"layers": [
"top",
"inner2",
"inner4",
"bottom"
],
"viaCost": 60
},
{
"name": "USBCP_VDDD_D",
"net": "PD_VDDD",
"width": 0.15,
"from": [
"C_PD_VDDD_HF2",
"pin2"
],
"fromSel": ".Power_input > .C_PD_VDDD_HF2 > .pin2",
"to": [
"R_PD_ISNK_UP",
"pin1"
],
"toSel": ".Power_input > .R_PD_ISNK_UP > .pin1",
"layers": [
"top",
"inner2",
"inner4",
"bottom"
],
"viaCost": 60
},
{
"name": "USBCP_VDDD_E",
"net": "PD_VDDD",
"width": 0.12,
"from": [
"U_PD",
"12"
],
"fromSel": ".Power_input > .U_PD > .12",
"to": [
"U_PD",
"13"
],
"toSel": ".Power_input > .U_PD > .13",
"layers": [
"top",
"inner2",
"inner4",
"bottom"
],
"viaCost": 60
},
{
"name": "USBCP_VDDD_F",
"net": "PD_VDDD",
"width": 0.12,
"from": [
"U_PD",
"12"
],
"fromSel": ".Power_input > .U_PD > .12",
"to": [
"R_PD_ISNK_UP",
"pin1"
],
"toSel": ".Power_input > .R_PD_ISNK_UP > .pin1",
"layers": [
"top",
"inner2",
"inner4",
"bottom"
],
"viaCost": 60
},
{
"name": "USBCP_VCCD",
"net": "PD_VCCD",
"width": 0.2,
"from": [
"U_PD",
"24"
],
"fromSel": ".Power_input > .U_PD > .24",
"to": [
"C_PD_VCCD",
"pin2"
],
"toSel": ".Power_input > .C_PD_VCCD > .pin2",
"layers": [
"top",
"inner2",
"inner4",
"bottom"
],
"viaCost": 60
},
{
"name": "USBCP_PD_GND_1",
"net": "GND",
"width": 0.15,
"from": [
"U_PD",
"1"
],
"fromSel": ".Power_input > .U_PD > .1",
"to": [
"U_PD",
"25"
],
"toSel": ".Power_input > .U_PD > .25",
"layers": [
"top"
],
"viaCost": 60
},
{
"name": "USBCP_PD_GND_2",
"net": "GND",
"width": 0.15,
"from": [
"U_PD",
"2"
],
"fromSel": ".Power_input > .U_PD > .2",
"to": [
"U_PD",
"25"
],
"toSel": ".Power_input > .U_PD > .25",
"layers": [
"top"
],
"viaCost": 60
},
{
"name": "USBCP_PD_GND_6",
"net": "GND",
"width": 0.15,
"from": [
"U_PD",
"6"
],
"fromSel": ".Power_input > .U_PD > .6",
"to": [
"U_PD",
"25"
],
"toSel": ".Power_input > .U_PD > .25",
"layers": [
"top"
],
"viaCost": 60
},
{
"name": "USBCP_PD_GND_19",
"net": "GND",
"width": 0.15,
"from": [
"U_PD",
"19"
],
"fromSel": ".Power_input > .U_PD > .19",
"to": [
"U_PD",
"25"
],
"toSel": ".Power_input > .U_PD > .25",
"layers": [
"top"
],
"viaCost": 60
},
{
"name": "USBCP_PD_GND_22",
"net": "GND",
"width": 0.15,
"from": [
"U_PD",
"22"
],
"fromSel": ".Power_input > .U_PD > .22",
"to": [
"U_PD",
"25"
],
"toSel": ".Power_input > .U_PD > .25",
"layers": [
"top"
],
"viaCost": 60
},
{
"name": "USBCP_PD_EP_GND",
"net": "GND",
"width": 0.3,
"from": [
"U_PD",
"25"
],
"fromSel": ".Power_input > .U_PD > .25",
"layers": [
"top"
],
"minViaDist": 0.45
},
{
"name": "USBCP_C_PD_VBUS_GND",
"net": "GND",
"width": 0.2,
"from": [
"C_PD_VBUS",
"pin1"
],
"fromSel": ".Power_input > .C_PD_VBUS > .pin1",
"layers": [
"top"
],
"minViaDist": 0.45
},
{
"name": "USBCP_C_PD_VDDD_GND",
"net": "GND",
"width": 0.2,
"from": [
"C_PD_VDDD",
"pin1"
],
"fromSel": ".Power_input > .C_PD_VDDD > .pin1",
"layers": [
"top"
],
"minViaDist": 0.45
},
{
"name": "USBCP_C_PD_VDDD_HF1_GND",
"net": "GND",
"width": 0.2,
"from": [
"C_PD_VDDD_HF1",
"pin1"
],
"fromSel": ".Power_input > .C_PD_VDDD_HF1 > .pin1",
"layers": [
"top"
],
"minViaDist": 0.45
},
{
"name": "USBCP_C_PD_VDDD_HF2_GND",
"net": "GND",
"width": 0.2,
"from": [
"C_PD_VDDD_HF2",
"pin1"
],
"fromSel": ".Power_input > .C_PD_VDDD_HF2 > .pin1",
"layers": [
"top"
],
"minViaDist": 0.45
},
{
"name": "USBCP_C_PD_VCCD_GND",
"net": "GND",
"width": 0.2,
"from": [
"C_PD_VCCD",
"pin1"
],
"fromSel": ".Power_input > .C_PD_VCCD > .pin1",
"layers": [
"top"
],
"minViaDist": 0.45
},
{
"name": "USBCP_R_PD_ISNK_DN_GND",
"net": "GND",
"width": 0.2,
"from": [
"R_PD_ISNK_DN",
"pin1"
],
"fromSel": ".Power_input > .R_PD_ISNK_DN > .pin1",
"layers": [
"top"
],
"minViaDist": 0.45
},
{
"name": "USBCP_NOR_IN1_GND",
"net": "GND",
"width": 0.2,
"from": [
"U_TYPEC_NOR",
"1"
],
"fromSel": ".Power_input > .U_TYPEC_NOR > .1",
"layers": [
"top"
],
"minViaDist": 0.45
},
{
"name": "USBCP_NOR_IN2_GND",
"net": "GND",
"width": 0.2,
"from": [
"U_TYPEC_NOR",
"6"
],
"fromSel": ".Power_input > .U_TYPEC_NOR > .6",
"layers": [
"top"
],
"minViaDist": 0.45
},
{
"name": "USBCP_USB0_DP_CPU",
"net": "USB0_DP",
"width": 0.12,
"from": [
"U1",
"N17"
],
"fromSel": ".Processor > .U1 > .N17",
"to": [
"U_PROG_ESD",
"1"
],
"toSel": ".USB_prog > .U_PROG_ESD > .1",
"layers": [
"top",
"inner2",
"inner4",
"bottom"
],
"viaCost": 150
},
{
"name": "USBCP_USB0_DM_CPU",
"net": "USB0_DM",
"width": 0.12,
"from": [
"U1",
"N18"
],
"fromSel": ".Processor > .U1 > .N18",
"to": [
"U_PROG_ESD",
"2"
],
"toSel": ".USB_prog > .U_PROG_ESD > .2",
"layers": [
"top",
"inner2",
"inner4",
"bottom"
],
"viaCost": 150
},
{
"name": "USBCP_USB0_DP_CONN",
"net": "USB0_DP",
"width": 0.12,
"from": [
"U_PROG_ESD",
"1"
],
"fromSel": ".USB_prog > .U_PROG_ESD > .1",
"to": [
"J_USB_PROG",
"A6"
],
"toSel": ".USB_prog > .J_USB_PROG > .A6",
"layers": [
"top",
"inner2",
"inner4",
"bottom"
],
"viaCost": 150
},
{
"name": "USBCP_USB0_DM_CONN",
"net": "USB0_DM",
"width": 0.12,
"from": [
"U_PROG_ESD",
"2"
],
"fromSel": ".USB_prog > .U_PROG_ESD > .2",
"to": [
"J_USB_PROG",
"A7"
],
"toSel": ".USB_prog > .J_USB_PROG > .A7",
"layers": [
"top",
"inner2",
"inner4",
"bottom"
],
"viaCost": 150
},
{
"name": "USBCP_USB0_DP_FLIP",
"net": "USB0_DP",
"width": 0.12,
"from": [
"J_USB_PROG",
"A6"
],
"fromSel": ".USB_prog > .J_USB_PROG > .A6",
"to": [
"J_USB_PROG",
"B6"
],
"toSel": ".USB_prog > .J_USB_PROG > .B6",
"layers": [
"top",
"inner2",
"inner4",
"bottom"
],
"viaCost": 60
},
{
"name": "USBCP_USB0_DM_FLIP",
"net": "USB0_DM",
"width": 0.12,
"from": [
"J_USB_PROG",
"A7"
],
"fromSel": ".USB_prog > .J_USB_PROG > .A7",
"to": [
"J_USB_PROG",
"B7"
],
"toSel": ".USB_prog > .J_USB_PROG > .B7",
"layers": [
"top",
"inner2",
"inner4",
"bottom"
],
"viaCost": 60
},
{
"name": "USBCP_USB0_VBUS_JOIN",
"net": "USB0_VBUS",
"width": 0.2,
"from": [
"J_USB_PROG",
"A4"
],
"fromSel": ".USB_prog > .J_USB_PROG > .A4",
"to": [
"J_USB_PROG",
"A9"
],
"toSel": ".USB_prog > .J_USB_PROG > .A9",
"layers": [
"top",
"inner2",
"inner4",
"bottom"
],
"viaCost": 60
},
{
"name": "USBCP_USB0_VBUS_CPU",
"net": "USB0_VBUS",
"width": 0.1,
"from": [
"U1",
"P15"
],
"fromSel": ".Processor > .U1 > .P15",
"to": [
"J_USB_PROG",
"A4"
],
"toSel": ".USB_prog > .J_USB_PROG > .A4",
"layers": [
"top",
"inner2",
"inner4",
"bottom"
],
"viaCost": 60,
"clearance": 0.1
},
{
"name": "USBCP_PROG_CC1",
"net": "USB_PROG_CC1",
"width": 0.12,
"from": [
"J_USB_PROG",
"A5"
],
"fromSel": ".USB_prog > .J_USB_PROG > .A5",
"to": [
"R_PROG_CC1",
"pin1"
],
"toSel": ".USB_prog > .R_PROG_CC1 > .pin1",
"layers": [
"top",
"inner2",
"inner4",
"bottom"
],
"viaCost": 60
},
{
"name": "USBCP_PROG_CC2",
"net": "USB_PROG_CC2",
"width": 0.12,
"from": [
"J_USB_PROG",
"B5"
],
"fromSel": ".USB_prog > .J_USB_PROG > .B5",
"to": [
"R_PROG_CC2",
"pin1"
],
"toSel": ".USB_prog > .R_PROG_CC2 > .pin1",
"layers": [
"top",
"inner2",
"inner4",
"bottom"
],
"viaCost": 60
},
{
"name": "USBCP_J_USB_PROG_A1_GND",
"net": "GND",
"width": 0.25,
"from": [
"J_USB_PROG",
"A1"
],
"fromSel": ".USB_prog > .J_USB_PROG > .A1",
"layers": [
"top"
],
"minViaDist": 0.45
},
{
"name": "USBCP_J_USB_PROG_A12_GND",
"net": "GND",
"width": 0.25,
"from": [
"J_USB_PROG",
"A12"
],
"fromSel": ".USB_prog > .J_USB_PROG > .A12",
"layers": [
"top"
],
"minViaDist": 0.45
},
{
"name": "USBCP_R_PROG_CC1_pin2_GND",
"net": "GND",
"width": 0.25,
"from": [
"R_PROG_CC1",
"pin2"
],
"fromSel": ".USB_prog > .R_PROG_CC1 > .pin2",
"layers": [
"top"
],
"minViaDist": 0.45
},
{
"name": "USBCP_R_PROG_CC2_pin2_GND",
"net": "GND",
"width": 0.25,
"from": [
"R_PROG_CC2",
"pin2"
],
"fromSel": ".USB_prog > .R_PROG_CC2 > .pin2",
"layers": [
"top"
],
"minViaDist": 0.45
},
{
"name": "USBCP_U_PROG_ESD_3_GND",
"net": "GND",
"width": 0.25,
"from": [
"U_PROG_ESD",
"3"
],
"fromSel": ".USB_prog > .U_PROG_ESD > .3",
"layers": [
"top"
],
"minViaDist": 0.45
},
{
"name": "USBCP_U_PROG_ESD_8_GND",
"net": "GND",
"width": 0.25,
"from": [
"U_PROG_ESD",
"8"
],
"fromSel": ".USB_prog > .U_PROG_ESD > .8",
"layers": [
"top"
],
"minViaDist": 0.45
}
]
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