0hmX/am3352-ddr-track-a-local-dfm-wip-20261007
Experimental RJ45-corrected board with isolated PG indication. 1005/1005 source joins pass; 15 expanded-guard physical errors, sourcing and qualification gates remain. Not fabrication-ready.
- Version
- 0.0.14
- License
- unset
- Stars
- 0
layout/CloudV1V8PowerRoutes.tsx
// Staged supply candidate; native emitted width and physical connectivity require joint verification.
const vias=[
{
"net": "V1V8",
"selector": ".Processor > .U1 > .N6",
"x": 2.8000000000000003,
"y": -2.8000000000000003,
"layer": "top",
"shape": "circle",
"radius": 0.2,
"padId": "pcb_smtpad_102",
"toLayer": "inner5",
"viaName": "PWR_V2_V1V8_1"
},
{
"net": "V1V8",
"selector": ".Processor > .U1 > .D7",
"x": -4.4,
"y": -2,
"layer": "top",
"shape": "circle",
"radius": 0.2,
"padId": "pcb_smtpad_111",
"toLayer": "inner5",
"viaName": "PWR_V2_V1V8_2"
},
{
"net": "V1V8",
"selector": ".Processor > .U1 > .E7",
"x": -3.6,
"y": -2,
"layer": "top",
"shape": "circle",
"radius": 0.2,
"padId": "pcb_smtpad_112",
"toLayer": "inner5",
"viaName": "PWR_V2_V1V8_3"
},
{
"net": "V1V8",
"selector": ".Processor > .U1 > .F9",
"x": -2.8000000000000003,
"y": -0.4,
"layer": "top",
"shape": "circle",
"radius": 0.2,
"padId": "pcb_smtpad_149",
"toLayer": "inner5",
"viaName": "PWR_V2_V1V8_5"
},
{
"net": "V1V8",
"selector": ".Processor > .U1 > .P9",
"x": 3.6,
"y": -0.4,
"layer": "top",
"shape": "circle",
"radius": 0.2,
"padId": "pcb_smtpad_157",
"toLayer": "inner5",
"viaName": "PWR_V2_V1V8_6"
},
{
"net": "V1V8",
"selector": ".Processor > .U1 > .D10",
"x": -4.4,
"y": 0.4,
"layer": "top",
"shape": "circle",
"radius": 0.2,
"padId": "pcb_smtpad_165",
"toLayer": "inner5",
"viaName": "PWR_V2_V1V8_7"
},
{
"net": "V1V8",
"selector": ".Processor > .U1 > .R10",
"x": 4.4,
"y": 0.4,
"layer": "top",
"shape": "circle",
"radius": 0.2,
"padId": "pcb_smtpad_176",
"toLayer": "inner5",
"viaName": "PWR_V2_V1V8_8"
},
{
"net": "V1V8",
"selector": ".Processor > .U1 > .R11",
"x": 4.4,
"y": 1.2000000000000002,
"layer": "top",
"shape": "circle",
"radius": 0.2,
"padId": "pcb_smtpad_194",
"toLayer": "inner5",
"viaName": "PWR_V2_V1V8_9"
},
{
"net": "V1V8",
"selector": ".Processor > .U1 > .E14",
"x": -3.6,
"y": 3.6,
"layer": "top",
"shape": "circle",
"radius": 0.2,
"padId": "pcb_smtpad_238",
"toLayer": "inner5",
"viaName": "PWR_V2_V1V8_11"
},
{
"net": "V1V8",
"selector": ".Processor > .U1 > .P14",
"x": 3.6,
"y": 3.6,
"layer": "top",
"shape": "circle",
"radius": 0.2,
"padId": "pcb_smtpad_247",
"toLayer": "inner5",
"viaName": "PWR_V2_V1V8_12"
},
{
"net": "V1V8",
"selector": ".Processor > .U1 > .N16",
"x": 2.8000000000000003,
"y": 5.2,
"layer": "top",
"shape": "circle",
"radius": 0.2,
"padId": "pcb_smtpad_282",
"toLayer": "inner5",
"viaName": "PWR_V2_V1V8_14"
},
{
"net": "V1V8",
"selector": ".Processor > .U1 > .R16",
"x": 4.4,
"y": 5.2,
"layer": "top",
"shape": "circle",
"radius": 0.2,
"padId": "pcb_smtpad_284",
"toLayer": "inner5",
"viaName": "PWR_V2_V1V8_15"
},
{
"net": "V1V8",
"selector": ".Processor > .C_VDDS_0 > .pin1",
"x": -6.24,
"y": -1,
"layer": "bottom",
"shape": "rect",
"width": 0.54,
"height": 0.64,
"padId": "pcb_smtpad_356",
"toLayer": "inner5",
"viaName": "PWR_V2_V1V8_17"
},
{
"net": "V1V8",
"selector": ".Processor > .C_VDDS_2 > .pin1",
"x": -0.74,
"y": 0,
"layer": "bottom",
"shape": "rect",
"width": 0.54,
"height": 0.64,
"padId": "pcb_smtpad_360",
"toLayer": "inner5",
"viaName": "PWR_V2_V1V8_19"
},
{
"net": "V1V8",
"selector": ".Processor > .C_SRAM_CORE_B > .pin1",
"x": 4.4125,
"y": -0.5,
"layer": "bottom",
"shape": "rect",
"width": 1.025,
"height": 1.4,
"padId": "pcb_smtpad_364",
"toLayer": "inner5",
"viaName": "PWR_V2_V1V8_21"
},
{
"net": "V1V8",
"selector": ".Processor > .C_SRAM_MPU_B > .pin1",
"x": 8.4125,
"y": -0.25,
"layer": "bottom",
"shape": "rect",
"width": 1.025,
"height": 1.4,
"padId": "pcb_smtpad_368",
"toLayer": "inner5",
"viaName": "PWR_V2_V1V8_23"
},
{
"net": "V1V8",
"selector": ".Processor > .C_VDDS_PLL_DDR > .pin1",
"x": 14.01,
"y": -11,
"layer": "bottom",
"shape": "rect",
"width": 0.54,
"height": 0.64,
"padId": "pcb_smtpad_416",
"toLayer": "inner5",
"viaName": "PWR_V2_V1V8_25"
},
{
"net": "V1V8",
"selector": ".Processor > .C_VDDS_PLL_CORE_LCD > .pin1",
"x": 14.01,
"y": -12.5,
"layer": "bottom",
"shape": "rect",
"width": 0.54,
"height": 0.64,
"padId": "pcb_smtpad_418",
"toLayer": "inner5",
"viaName": "PWR_V2_V1V8_26"
},
{
"net": "V1V8",
"selector": ".Processor > .C_VDDS_OSC > .pin1",
"x": -3.49,
"y": -3,
"layer": "bottom",
"shape": "rect",
"width": 0.54,
"height": 0.64,
"padId": "pcb_smtpad_422",
"toLayer": "inner5",
"viaName": "PWR_V2_V1V8_28"
},
{
"net": "V1V8",
"selector": ".Processor > .C_VDDS_RTC > .pin1",
"x": -10.99,
"y": -8.25,
"layer": "bottom",
"shape": "rect",
"width": 0.54,
"height": 0.64,
"padId": "pcb_smtpad_424",
"toLayer": "inner5",
"viaName": "PWR_V2_V1V8_29"
},
{
"net": "V1V8",
"selector": ".Processor > .C_VDDA1P8V_USB0 > .pin1",
"x": 5.51,
"y": 8.2,
"layer": "bottom",
"shape": "rect",
"width": 0.54,
"height": 0.64,
"padId": "pcb_smtpad_426",
"toLayer": "inner5",
"viaName": "PWR_V2_V1V8_30"
},
{
"net": "V1V8",
"selector": ".Processor > .C_VDDA1P8V_USB1 > .pin1",
"x": 4.01,
"y": -2.25,
"layer": "bottom",
"shape": "rect",
"width": 0.54,
"height": 0.64,
"padId": "pcb_smtpad_428",
"toLayer": "inner5",
"viaName": "PWR_V2_V1V8_31"
},
{
"net": "V1V8",
"selector": ".Power_management > .C_PWR12_B > .pin1",
"x": 10.35,
"y": -5.2,
"layer": "top",
"shape": "rect",
"width": 2.7,
"height": 1.15,
"padId": "pcb_smtpad_713",
"toLayer": "inner5",
"viaName": "PWR_V2_V1V8_33"
},
{
"net": "V1V8",
"selector": ".Power_management > .C_PWR12 > .pin1",
"x": 17.5,
"y": -3.3,
"layer": "bottom",
"shape": "rect",
"width": 2.7,
"height": 1.15,
"padId": "pcb_smtpad_715",
"toLayer": "inner5",
"viaName": "PWR_V2_V1V8_34"
},
{
"net": "V1V8",
"selector": ".Power_management > .R_RTC_RESET > .pin1",
"x": 15.99,
"y": -14,
"layer": "top",
"shape": "rect",
"width": 0.54,
"height": 0.64,
"padId": "pcb_smtpad_737",
"toLayer": "inner5",
"viaName": "PWR_V2_V1V8_35"
},
{
"net": "V1V8",
"selector": ".Power_management > .U_RTC_RESET_DELAY > .3",
"x": 8.6,
"y": 10.175,
"layer": "top",
"shape": "rect",
"width": 0.6,
"height": 0.31,
"padId": "pcb_smtpad_749",
"toLayer": "inner5",
"viaName": "PWR_V2_V1V8_37"
},
{
"net": "V1V8",
"selector": ".Power_management > .U_RTC_POR_GATE > .5",
"x": 6.6375,
"y": 11.45,
"layer": "top",
"shape": "rect",
"width": 1.325,
"height": 0.6,
"padId": "pcb_smtpad_764",
"toLayer": "inner5",
"viaName": "PWR_V2_V1V8_38"
},
{
"net": "V1V8",
"selector": ".Power_management > .C_RTC_RESET_BYP > .pin1",
"x": 15.99,
"y": -15.5,
"layer": "top",
"shape": "rect",
"width": 0.54,
"height": 0.64,
"padId": "pcb_smtpad_765",
"toLayer": "inner5",
"viaName": "PWR_V2_V1V8_39"
},
{
"net": "V1V8",
"selector": ".Power_management > .C_RTC_GATE_BYP > .pin1",
"x": 16.74,
"y": -17,
"layer": "top",
"shape": "rect",
"width": 0.54,
"height": 0.64,
"padId": "pcb_smtpad_767",
"toLayer": "inner5",
"viaName": "PWR_V2_V1V8_40"
},
{
"net": "V1V8",
"selector": ".Boot_and_clock > .C_CLOCK_GATE > .pin1",
"x": 7.6899999999999995,
"y": -17,
"layer": "top",
"shape": "rect",
"width": 0.54,
"height": 0.64,
"padId": "pcb_smtpad_822",
"toLayer": "inner5",
"viaName": "PWR_V2_V1V8_44"
},
{
"net": "V1V8",
"selector": ".Ethernet_and_RGB_expansion > .C_RMII_RETURN_A > .pin2",
"x": 21,
"y": 11.99,
"layer": "bottom",
"shape": "rect",
"width": 0.64,
"height": 0.54,
"padId": "pcb_smtpad_1147",
"toLayer": "inner5",
"viaName": "PWR_V2_V1V8_45"
},
{
"net": "V1V8",
"selector": ".Ethernet_and_RGB_expansion > .C_RMII_RETURN_B > .pin2",
"x": 16.1,
"y": 11.99,
"layer": "bottom",
"shape": "rect",
"width": 0.64,
"height": 0.54,
"padId": "pcb_smtpad_1149",
"toLayer": "inner5",
"viaName": "PWR_V2_V1V8_46"
},
{
"net": "V1V8",
"selector": ".Ethernet_and_RGB_expansion > .C_RMII_RETURN_C > .pin2",
"x": 24.79,
"y": 10,
"layer": "bottom",
"shape": "rect",
"width": 0.54,
"height": 0.64,
"padId": "pcb_smtpad_1151",
"toLayer": "inner5",
"viaName": "PWR_V2_V1V8_47"
},
{
"net": "V1V8",
"selector": ".Ethernet_and_RGB_expansion > .C_RMII_RETURN_D > .pin2",
"x": 31.24,
"y": 3.765,
"layer": "bottom",
"shape": "rect",
"width": 0.54,
"height": 0.64,
"padId": "pcb_smtpad_1153",
"toLayer": "inner5",
"viaName": "PWR_V2_V1V8_48"
},
{
"net": "V1V8",
"selector": ".Debug_status > .TP_DBG_V1V8 > .V1V8",
"x": 13.99,
"y": -16,
"layer": "top",
"shape": "circle",
"radius": 0.6,
"padId": "pcb_smtpad_1156",
"toLayer": "inner5",
"viaName": "PWR_V2_V1V8_49"
},
{
"net": "V1V8",
"selector": ".Power_management > .U_PMIC > .4",
"x": 18.0625,
"y": -1,
"layer": "top",
"shape": "rect",
"width": 0.825,
"height": 0.2,
"padId": "pcb_smtpad_631",
"toLayer": "inner5",
"viaName": "V1V8_PMIC_FEED"
},
{
"net": "V1V8",
"selector": ".Boot_and_clock > .Y_SOC > .4",
"x": 6.1499999999999995,
"y": -9.075,
"layer": "top",
"shape": "rect",
"width": 1.1,
"height": 1,
"padId": "pcb_smtpad_808",
"toLayer": "inner5",
"viaName": "V1V8_Y_SOC_FEED",
"pendingSignalAccess": true
},
{
"selector": ".Processor > .C_VDDS_B > .pin1",
"x": 9.4125,
"y": 1.75,
"layer": "bottom",
"shape": "rect",
"width": 1.025,
"height": 1.4,
"padId": "pcb_smtpad_354",
"net": "V1V8",
"toLayer": "inner5",
"viaName": "V1V8_ADDITIONAL_38"
},
{
"selector": ".Processor > .C_VDDS_3 > .pin1",
"x": 8.76,
"y": 3.5,
"layer": "bottom",
"shape": "rect",
"width": 0.54,
"height": 0.64,
"padId": "pcb_smtpad_362",
"net": "V1V8",
"toLayer": "inner5",
"viaName": "V1V8_ADDITIONAL_39"
},
{
"selector": ".Processor > .C_SRAM_CORE_0 > .pin1",
"x": 6.26,
"y": 2,
"layer": "bottom",
"shape": "rect",
"width": 0.54,
"height": 0.64,
"padId": "pcb_smtpad_366",
"net": "V1V8",
"toLayer": "inner5",
"viaName": "V1V8_ADDITIONAL_40"
}
] as const
const routes=[
{
"name": "CLOUD_V1V8_V2_0",
"net": "V1V8",
"from": ".Processor > .U1 > .E9",
"to": ".Processor > .U1 > .F9",
"width": 0.3,
"layer": "top",
"points": [
[
-3.6,
-0.4
],
[
-2.8000000000000003,
-0.4
]
]
},
{
"name": "CLOUD_V1V8_V2_1",
"net": "V1V8",
"from": ".Processor > .U1 > .R10",
"to": ".Processor > .U1 > .R11",
"width": 0.3,
"layer": "top",
"points": [
[
4.4,
0.4
],
[
4.4,
1.2000000000000002
]
]
},
{
"name": "CLOUD_V1V8_V2_2",
"net": "V1V8",
"from": ".Processor > .U1 > .D7",
"to": ".Processor > .U1 > .E7",
"width": 0.3,
"layer": "top",
"points": [
[
-4.4,
-2
],
[
-3.6,
-2
]
]
},
{
"name": "CLOUD_V1V8_V2_3",
"net": "V1V8",
"from": ".Processor > .U1 > .E9",
"to": ".Processor > .U1 > .D10",
"width": 0.3,
"layer": "top",
"points": [
[
-3.6,
-0.4
],
[
-4.4,
0.4
]
]
},
{
"name": "CLOUD_V1V8_V2_4",
"net": "V1V8",
"from": ".Processor > .C_VDDS_PLL_MPU > .pin1",
"to": ".Processor > .C_VDDS_RTC > .pin1",
"width": 0.3,
"layer": "bottom",
"points": [
[
-10.99,
-9.5
],
[
-10.99,
-8.25
]
]
},
{
"name": "CLOUD_V1V8_V2_5",
"net": "V1V8",
"from": ".Power_management > .U_RTC_RESET_DELAY > .1",
"to": ".Power_management > .U_RTC_RESET_DELAY > .3",
"width": 0.3,
"layer": "top",
"points": [
[
8.6,
11.475
],
[
8.0,
11.100000000000001
],
[
8.0,
10.5
],
[
8.6,
10.175
]
]
},
{
"name": "CLOUD_V1V8_V2_6",
"net": "V1V8",
"from": "PWR_V2_V1V8_35.inner5",
"to": "PWR_V2_V1V8_39.inner5",
"width": 0.3,
"layer": "inner5",
"points": [
[
15.99,
-14
],
[
15.99,
-15.5
]
]
},
{
"name": "CLOUD_V1V8_V2_7",
"net": "V1V8",
"from": ".Boot_and_clock > .C_SOC_CLOCK > .pin1",
"to": ".Boot_and_clock > .U_CLOCK_GATE > .5",
"width": 0.3,
"layer": "top",
"points": [
[
5.99,
-14.5
],
[
6.1375,
-16.05
]
]
},
{
"name": "CLOUD_V1V8_V2_8",
"net": "V1V8",
"from": ".Processor > .C_SRAM_CORE_B > .pin1",
"to": ".Processor > .C_VDDA1P8V_USB1 > .pin1",
"width": 0.3,
"layer": "bottom",
"points": [
[
4.4125,
-0.5
],
[
4.01,
-2.25
]
]
},
{
"name": "CLOUD_V1V8_V2_9",
"net": "V1V8",
"from": ".Boot_and_clock > .U_CLOCK_GATE > .5",
"to": ".Boot_and_clock > .C_CLOCK_GATE > .pin1",
"width": 0.3,
"layer": "top",
"points": [
[
6.1375,
-16.05
],
[
7.6899999999999995,
-17
]
]
},
{
"name": "CLOUD_V1V8_V2_10",
"net": "V1V8",
"from": ".Processor > .C_VDDS_B > .pin1",
"to": ".Processor > .C_VDDS_3 > .pin1",
"width": 0.3,
"layer": "bottom",
"points": [
[
9.4125,
1.75
],
[
8.76,
3.5
]
]
},
{
"name": "CLOUD_V1V8_V2_11",
"net": "V1V8",
"from": ".Power_management > .C_RTC_RESET_BYP > .pin1",
"to": ".Debug_status > .TP_DBG_V1V8 > .V1V8",
"width": 0.3,
"layer": "top",
"points": [
[
15.99,
-15.5
],
[
13.99,
-16
]
]
},
{
"name": "CLOUD_V1V8_V2_12",
"net": "V1V8",
"from": "V1V8_ADDITIONAL_38.inner5",
"to": "PWR_V2_V1V8_23.inner5",
"width": 0.3,
"layer": "inner5",
"points": [
[
9.4125,
1.75
],
[
9.399999999999999,
1.5
],
[
9.399999999999999,
0.3500000000000014
],
[
9.600000000000001,
0.14999999999999858
],
[
9.600000000000001,
-0.3500000000000014
],
[
9.399999999999999,
-0.5499999999999972
],
[
8.700000000000003,
-0.5499999999999972
],
[
8.399999999999999,
-0.25
],
[
8.4125,
-0.25
]
]
},
{
"name": "CLOUD_V1V8_V2_13",
"net": "V1V8",
"from": "V1V8_ADDITIONAL_39.inner5",
"to": "V1V8_ADDITIONAL_40.inner5",
"width": 0.3,
"layer": "inner5",
"points": [
[
8.76,
3.5
],
[
6.76,
3.5
],
[
6.26,
3.0
],
[
6.26,
2
]
]
},
{
"name": "CLOUD_V1V8_V2_14",
"net": "V1V8",
"from": ".Processor > .C_VDDS_B > .pin1",
"to": ".Processor > .C_SRAM_MPU_0 > .pin1",
"width": 0.3,
"layer": "bottom",
"points": [
[
9.4125,
1.75
],
[
11.700000000000003,
1.8999999999999986
],
[
12.26,
2.5
]
]
},
{
"name": "CLOUD_V1V8_V2_15",
"net": "V1V8",
"from": ".Processor > .C_SRAM_CORE_B > .pin1",
"to": ".Processor > .C_SRAM_CORE_0 > .pin1",
"width": 0.3,
"layer": "bottom",
"points": [
[
4.4125,
-0.5
],
[
5.899999999999999,
0.7000000000000028
],
[
6.26,
2
]
]
},
{
"name": "CLOUD_V1V8_V2_19",
"net": "V1V8",
"from": "PWR_V2_V1V8_6.inner5",
"to": "PWR_V2_V1V8_21.inner5",
"width": 0.3,
"layer": "inner5",
"points": [
[
3.6,
-0.4
],
[
4.4125,
-0.5
]
]
},
{
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"x": 4.429263548302419,
"y": 5.052882207939516
},
{
"x": 4.4147025710494345,
"y": 5.050722290999171
},
{
"x": 4.4,
"y": 5.05
}
]
},
{
"name": "V1V8_E14_LINK_BODY",
"net": "V1V8",
"layer": "inner4",
"outline": [
{
"x": -3.5578798512195062,
"y": 3.3006987925431845
},
{
"x": -3.9,
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{
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},
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{
"x": -4.5,
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{
"x": -4.49951847266722,
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{
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{
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{
"x": -3.6289283540855157,
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"x": -3.61940642954349,
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},
{
"x": -3.609697610476327,
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},
{
"x": -3.599895398119024,
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},
{
"x": -3.5900941931350157,
"y": 3.6995081654456237
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"y": 3.6881427692015207
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{
"x": -3.544356033806634,
"y": 3.6830888020510075
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{
"x": -3.536479847942449,
"y": 3.6772346443157837
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{
"x": -3.5292153958662262,
"y": 3.670636674735048
},
{
"x": -3.522632638222612,
"y": 3.663358435362679
},
{
"x": -3.516794970566216,
"y": 3.6554700196225234
},
{
"x": -3.511758612827763,
"y": 3.647047397270406
},
{
"x": -3.507572067885428,
"y": 3.638171682763851
},
{
"x": -3.5042756544556037,
"y": 3.6289283540855157
},
{
"x": -3.5019011188016216,
"y": 3.61940642954349
},
{
"x": -3.5004713289998834,
"y": 3.609697610476327
},
{
"x": -3.5000000547077827,
"y": 3.599895398119024
},
{
"x": -3.5004918345543765,
"y": 3.5900941931350157
},
{
"x": -3.501941932430908,
"y": 3.5803883864861823
}
]
}
] as const
export function CloudV1V8PowerRoutes(){return <>
{vias.map(v=><via key={v.viaName} name={v.viaName} pcbX={v.x} pcbY={v.y} fromLayer={v.layer} toLayer={v.toLayer} holeDiameter={.15} outerDiameter={.30} connectsTo={v.selector}/>)}
{routes.map(r=><trace key={r.name} name={r.name} from={r.from} to={r.to} width={r.width} pcbPathRelativeTo=".Processor > .U1 > .A1" pcbPaths={[[r.from,...r.points.map(([x,y])=>({x,y})),r.to]]}/>)}
{strips.map(p=><copperpour key={p.name} name={p.name} layer={p.layer} connectsTo={`net.${p.net}`} clearance={.2} boardEdgeMargin={0} unbroken coveredWithSolderMask outline={p.outline}/>)}
</>}
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